Corner transistor suppression
View Patent ↗The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.
1. A device comprising:
a trench isolation region formed in a substrate, the trench isolation region comprising:
a trench having corners, side surfaces, and a bottom surface;
an oxide liner on the side surfaces and bottom surface of the trench;
high-K dielectric spacers formed only at upper corners of the trench, the high-K dielectric spacers having a triangular shape when viewed in cross-section;
a portion of a gate electrode filling a recess positioned only at the upper corners of the trench; and
insulating material filling the trench,
wherein the portion of the gate electrode is in direct contact with the insulating material and high-K dielectric spacers.
2. The device according to claim 1 , further comprising:
transistors on the substrate separated by the trench isolation region.
3. The device according to claim 2 , wherein the high-K dielectric spacers increase a threshold voltage of and lowers mobility of a parasitic transistor formed at a trench corner.
4. The device according to claim 1 , wherein the oxide liner is formed to a thickness of 10 to 40 Å.
5. The device according to claim 1 , wherein the high-k dielectric spacers are formed to a thickness of 20 to 80 Å.
6. A device comprising:
a trench isolation region formed in a substrate, the substrate having an upper surface, the trench isolation region comprising:
a trench having corners, side surfaces, and a bottom surface;
insulating material filling the trench;
a recess in the insulating material extending below the upper surface of the substrate;
high-K dielectric spacers formed in the recess only at upper corners of the trench the high-K dielectric spacers having a triangular shape when viewed in cross-section; and
a portion of a gate electrode filling a recess positioned only at the upper corners of the trench, in direct contact with the insulating material and high-K dielectric spacers.
7. The device according to claim 6 , further comprising:
an oxide liner on the side surfaces and bottom surface of the trench.
8. The device according to claim 7 , wherein the oxide liner is formed to a thickness of 10 to 40 Å.
9. The device according to claim 6 , wherein high-k dielectric spacers are formed to a thickness of 20 to 80 Å.
10. The device according to claim 6 , further comprising:
transistors on the substrate separated by the trench isolation region.
11. The device according to claim 6 , wherein the high-K dielectric spacers increase a threshold voltage of and lowers mobility of a parasitic transistor formed the trench corners.
12. The device according to claim 6 , wherein each high-K dielectric spacer is formed to a height and width of 20 to 80 Å.