IP Library Granted Patent US 8,158,513
Granted Patent B2
US 8,158,513 · App. 12/247,479 · Granted Apr 17, 2012

Integrated circuit system employing backside energy source for electrical contact formation

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Quick Facts
Patent No.
US 8,158,513
App. No.
12/247,479
Granted
Apr 17, 2012
Kind
B2
Abstract

A method for manufacturing an integrated circuit system includes: providing a first material; forming a second material over a first side of the first material; and exposing a second side of the first material to an energy source to form an electrical contact at an interface of the first material and the second material.

Claims (46)

1. A method for manufacturing an integrated circuit system comprising:

providing a first material;

forming a second material over a first side of the first material; and

exposing a second side of the first material to an energy source to raise a temperature of the second material higher than a temperature of the first material and to form an electrical contact at an interface of the first material and the second material, the energy source including a pulsed laser for controlling spiking or piping.

2. The method as claimed in claim 1 wherein:

providing the first material includes providing a material with transparent or semi-transparent properties to the energy source.

3. The method as claimed in claim 1 wherein:

forming the second material includes forming a metal layer.

4. The method as claimed in claim 1 wherein:

exposing the second side of the first material to the pulsed laser controls the diffusion of the second material by controlling the vertical temperature profile from the second material to the first material.

5. The method as claimed in claim 1 wherein:

exposing the second side of the first material to the energy source to form the electrical contact includes forming a silicide contact or a salicide contact.

6. A method for manufacturing an integrated circuit system comprising:

providing a substrate;

forming a metal layer over the substrate; and

exposing a backside of the substrate to an energy source to raise a temperature of the metal layer higher than a temperature of the substrate and to form an electrical contact, the energy source including a pulsed laser for controlling spiking or piping.

7. The method as claimed in claim 6 wherein:

providing the substrate includes providing a silicon material.

8. The method as claimed in claim 6 wherein:

forming the metal layer over the substrate includes forming a refractory metal.

9. The method as claimed in claim 6 wherein:

exposing the backside of the substrate to the energy source includes using a form of energy with a wavelength exceeding approximately 1 micrometer.

10. The method as claimed in claim 6 wherein:

exposing the backside of the substrate to the energy source to form the electrical contact includes forming the electrical contact over a source/drain.

11. A method for manufacturing an integrated circuit system comprising:

providing a substrate including an active device;

forming a metal layer over the substrate and the active device; and

exposing a backside of the substrate to an energy source to raise a temperature of the metal layer higher than a temperature of the substrate to form an electrical contact, the energy source including a pulsed laser for controlling spiking or piping.

12. The method as claimed in claim 11 wherein:

providing the active device includes providing an NMOS device.

13. The method as claimed in claim 11 wherein:

providing the active device includes providing a PMOS device.

14. The method as claimed in claim 11 wherein:

providing the active device includes providing a CMOS device.

15. The method as claimed in claim 11 wherein:

providing the substrate includes the use of silicon.

16. The method as claimed in claim 11 wherein:

forming the metal layer includes forming a nickel layer.

17. The method as claimed in claim 11 wherein:

exposing the backside of the substrate to the energy source includes using a carbon dioxide pulsed laser.

18. The method as claimed in claim 11 wherein:

exposing the backside of the substrate to the energy source to form the electrical contact includes forming the electrical contact over a source/drain.

19. The method as claimed in claim 11 wherein:

exposing the backside of the substrate to the energy source to form the electrical contact includes forming a silicide contact or a salicide contact.

20. The method as claimed in claim 11 wherein:

exposing the backside of the substrate to the energy source helps to prevent forming a metal residue on a spacer.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2019
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: ALSEPHINA INNOVATIONS INC.
Reel/Frame 049669/0775 →
CHANGE OF NAME Recorded Nov 20, 2018
From: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 047614/0081 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2008
From: MAI, ZHIHONG; TOH, SUEY LI; TAN, PIK KEE; LAM, JEFFREY C.; HSIA, LIANG-CHOO
To: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
Reel/Frame 021647/0835 →