Semiconductor device and methods for forming a semiconductor device
View Patent ↗Devices and methods of forming a device are disclosed. A substrate prepared with at least a first transistor and a second transistor is provided. Each of the first and second transistors includes a gate disposed on the substrate between first and second contact regions in the substrate. A silicide block layer is formed on the substrate and is patterned to expose portions of the first and second contact regions. Silicide contacts are formed in the exposed first and second contact regions. The silicide contacts are displaced from sides of the gates of the first and second transistors. A contact dielectric layer is formed and contacts are formed in the contact dielectric layer. The contacts are in communication with the silicide contacts in the contact regions.
1. A method of forming a device comprising:
providing a substrate prepared with at least a first transistor and a second transistor, each of the first and second transistors having a gate disposed on the substrate between first and second heavily doped source/drain (S/D) regions in the substrate, wherein the heavily doped S/D regions are disposed adjacent to first and second sides of the gate and partially underlaps the gate;
forming a silicide block layer on the substrate, wherein the silicide block layer covers and in direct contact with the first and second sides and top surface of the gate and the first and second heavily doped S/D regions;
patterning the silicide block layer to expose portions of the first and second heavily doped S/D regions of the first and second transistors;
forming silicide contacts in the exposed portions of the first and second heavily doped S/D regions, wherein the patterned silicide block layer is in direct contact with sides and top surface of the gates when the silicide contacts are formed and the silicide contacts are displaced from the sides of the gates and sides of the first and second heavily doped S/D regions of the first and second transistors;
forming a contact dielectric layer covering the at least first and second transistors: and
forming contacts in the contact dielectric layer, wherein the contacts are in communication with the silicide contacts in the heavily doped S/D regions.
2. The method of claim 1 comprising:
forming a resist layer over and in direct contact with the silicide block layer prior to patterning the silicide block layer; and
patterning the resist layer to form openings corresponding to the first and second heavily doped S/D regions.
3. The method of claim 2 wherein:
the resist layer comprises an optical dispersive (OD) layer; and
the silicide block layer comprises nitride, oxide, oxynitride or a combination thereof.
4. The method of claim 3 wherein:
the first and second transistors comprise first and second split gate transistors, each of the split gate transistors comprises a select gate having a select gate electrode over a select gate dielectric, and a memory gate having a control gate stacked over a floating gate.
5. The method of claim 3 wherein patterning the resist layer comprises using a high wavelength excimer laser as a radiation source to expose the resist layer.
6. The method of claim 5 wherein the high wavelength excimer laser comprises KrF excimer laser.
7. The method of claim 5 comprising:
removing the resist layer after patterning the silicide block layer;
removing the silicide block layer after forming the silicide contacts; and wherein
the contact dielectric layer is in direct contact with the first and second sides and top surface of the gate of the first and second transistors after removing the silicide block layer.
8. The method of clam 3 wherein the first and second transistors comprise first and second split gate transistors, each of the split gate transistors comprises a select gate, a memory gate having a control gate stacked over a floating gate, and a gate spacer disposed between the select gate and memory gate.
9. The method of claim 2 wherein:
the first and second transistors comprise first and second split gate transistors, each of the split gate transistors comprises a select gate and a memory gate having a control gate stacked over a floating gate; and
the resist layer includes a thickness of about 1.5-2 times a height of the floating gate.
10. The method of claim 1 wherein displacement distance between the silicide contacts and sides of the gates is about 0.5 to 2 times a dimension of the contact in order to prevent electrical shorts or bridging with adjacent gates.
11. The method of claim 1 comprising:
forming a first resist layer over the silicide block layer prior to patterning the silicide block layer;
forming a hard mask layer over the first resist layer;
forming a second resist layer over the hard mask layer; and
patterning the second resist layer to form openings corresponding to the first and second heavily doped S/D regions.
12. The method of claim 11 wherein:
the first resist layer comprises an optical dispersive (OD) layer;
the hard mask layer comprises a material with high etch selectivity to the underlying OD layer; and
the silicide block layer comprises nitride, oxide, oxynitride or a combination thereof.
13. The method of claim 12 wherein patterning the second resist layer comprises using a low wavelength excimer laser as a radiation source to expose the second resist layer.
14. The method of claim 13 wherein the low wavelength excimer laser comprises ArF excimer laser.
15. The method of claim 12 comprising:
removing portions of the hard mask and OD layers unprotected by the second resist layer to expose portions of the silicide block layer above the first and second heavily doped S/D regions.
16. The method of claim 15 comprising:
removing the hard mask and OD layers after patterning the silicide block layer.
17. A method of forming a device comprising:
providing a substrate prepared with at least a first transistor wherein the first transistor comprises a gate disposed on the substrate between first and second heavily doped source/drain (S/D) regions in the substrate, wherein the heavily doped S/D regions are disposed adjacent to first and second sides of the gate and partially underlaps the gate;
forming a silicide block layer on the substrate, wherein the silicide block layer covers and in direct contact with the first and second sides and top surface of the gate and the first and second heavily doped S/D regions;
patterning the silicide block layer to expose portions of the heavily doped S/D regions of the first transistor; and
forming silicide contacts in the exposed portions of the first and second heavily doped S/D regions, wherein the patterned silicide block layer is in direct contact with sides and top surface of the gates when the silicide contacts are formed and the silicide contacts are displaced from the sides of the gate and sides of the first and second heavily doped S/D regions of the first transistor.
18. The method of claim 17 comprising:
forming a first resist layer over the silicide block layer prior to patterning the silicide block layer;
forming a hard mask layer over the first resist layer;
forming a second resist layer over the hard mask layer; and
patterning the second resist layer to form openings corresponding to the first and second heavily doped S/D regions.
19. A device comprising:
a substrate prepared with at least a first transistor and a second transistor, each of the first and second transistors comprises a gate disposed on the substrate between first and second heavily doped source/drain (S/D) regions in the substrate, wherein the heavily doped S/D regions are disposed adjacent to first and second sides of the gate and partially underlaps the gates;
silicide contacts disposed on portions of the first and second heavily doped S/D regions, wherein the silicide contacts are displaced from the first and second sides of the gates and sides of the first and second heavily doped S/D regions of the first and second transistors;
a contact dielectric layer disposed over the substrate covering the transistors, wherein the contact dielectric layer is in direct contact with at least the first and second sides and top surface of the gate of the first and second transistors; and
contacts disposed in the contact dielectric layer, wherein the contacts are in communication with the silicide contacts in the heavily doped S/D regions.
20. The device of claim 19 wherein displacement distance between the silicide contacts and sides of the gates is about 0.5 to 2 times a dimension of the contact in order to prevent electrical shorts or bridging with adjacent gates.
21. The method of claim 17 wherein the first transistor comprises a split gate transistor, the split gate transistor comprises a select gate, a memory gate having a control gate stacked over a floating gate, and a gate spacer disposed between the select gate and memory gate.