Integrated circuit system using dual damascene process

1. A method comprising:

providing a semiconductor substrate having a semiconductor device provided thereon;

forming a first dielectric layer over the semiconductor substrate;

forming a first conductor core in the first dielectric layer;

forming a stop layer over the first conductor core;

forming a second dielectric layer over the stop layer;

forming a channel and a via in the second dielectric layer and the via closed to the first conductor core;

wet cleaning the channel and the via in the second dielectric layer;

depositing a barrier metal layer in the channel and the via in the second dielectric layer;

selectively etching the barrier metal layer and the stop layer from the bottom of the via in the dielectric layer; and

forming a second conductor core over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

2. The method as claimed in claim 1 wherein depositing the second dielectric layer uses an ultra-low dielectric constant material.

3. The method as claimed in claim 1 wherein forming the first and second conductor cores deposits a material of at least one of copper, aluminum, gold, silver, compounds thereof, and combinations thereof.

4. The method as claimed in claim 1 , further comprising:

forming a pore sealant over the sidewalls of channel and the via in the second dielectric layer.

5. The method as claimed in claim 1 , wherein forming the second conductor core further comprises:

depositing a barrier metal flash layer over the barrier metal layer;

forming a metal seed layer over the barrier metal flash layer; and

forming a conductor metal over the metal seed layer.

6. The method as claimed in claim 1 , wherein forming a channel and a via in the second dielectric layer uses a dual damascene process.

7. The method as claimed in claim 1 , wherein wet cleaning the channel and the via is performed while the via is closed to contact with the first conductor core.

8. A method comprising:

providing a semiconductor substrate having a semiconductor device provided thereon;

forming a first dielectric layer over the semiconductor substrate;

forming a first conductor core in the first dielectric layer;

forming a stop layer over the first conductor core;

forming a second dielectric layer over the stop layer;

forming a channel and a via in the second dielectric layer and the via closed to the first conductor core;

wet cleaning the channel and the via in the second dielectric layer while the stop layer is present;

depositing a barrier metal layer to line the channel and the via in the second dielectric layer;

selectively etching the barrier metal layer and the stop layer from the bottom of the via in the dielectric layer only after wet cleaning the channel and the via;

then forming a second conductor core over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

9. The method as claimed in claim 8 , wherein depositing the second dielectric layer uses an ultra-low dielectric constant material.

10. The method as claimed in claim 8 , wherein forming the first and second conductor cores deposits a material of at least one of copper, aluminum, gold, silver, compounds thereof, and combinations thereof.

11. The method as claimed in claim 8 , further comprising:

forming a pore sealant over the sidewalls of the channel and the via in the second dielectric layer.

12. The method as claimed in claim 8 , wherein forming the second conductor core further comprises:

depositing a barrier metal flash layer over the barrier metal layer;

forming a metal seed layer over the barrier metal flash layer; and

forming a conductor metal over the metal seed layer.

13. The method as claimed in claim 8 , wherein forming a channel and a via in the second dielectric layer uses a dual damascene process.

14. A method for reducing contaminants in a via connecting a first and a second conductor cores in an integrated circuit, comprising:

forming a stop layer over the first conductor core;

forming a dielectric layer over the stop layer;

forming the via in the dielectric layer and in the stop layer closed to the first conductor core;

wet cleaning the via in the presence of the stop layer;

depositing a barrier metal layer to line the via;

selectively etching the barrier metal layer and the stop layer from the bottom of the via in the dielectric layer after wet cleaning the via;

then forming a second conductor core over the barrier metal layer to fill the via to connect the second conductor core to the first conductor core.

15. The method as claimed in claim 14 , wherein depositing the dielectric layer uses an ultra-low dielectric constant material.

16. The method for reducing contaminants as claimed in claim 14 , wherein the first and second conductor cores comprise a material of at least one of copper, aluminum, gold, silver, compounds thereof, and combinations thereof.

17. The method for reducing contaminants as claimed in claim 14 , further comprising:

forming a pore sealant over the sidewalls of the via.

18. The method for reducing contaminants as claimed in claim 14 , further comprising:

depositing a barrier metal flash layer over the barrier metal layer;

forming a metal seed layer over the barrier metal flash layer; and

forming a conductor metal over the metal seed layer.

19. The method for reducing contaminants as claimed in claim 14 , wherein wet cleaning the channel and the via is performed while the via is closed to contact with the first conductor core.

20. The method for reducing contaminants as claimed in claim 14 , wherein forming the via in the dielectric layer uses a dual damascene process.