Wafer processing
View Patent ↗Methods for forming a device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layers of the top and bottom pad stacks include an initial thickness T T1 and T B1 respectively. Trench isolation regions are formed in the substrate. The second pad layer of the top and bottom pad stacks are removed after forming the trench isolation regions by a batch wet etch process.
1. A method of forming a device comprising:
providing a substrate having top and bottom pad stacks, wherein each pad stack comprises at least first and second pad layers, and the second pad layers of the top and bottom pad stacks comprise an initial thickness T T1 and T B1 respectively;
forming shallow trench isolation (STI) regions in the substrate, wherein forming the STI regions comprises
patterning the top pad stack to form openings corresponding to the STI regions,
etching the substrate to form isolation trenches of the STI regions through the top pad stack openings, wherein etching the substrate removes exposed portions of the substrate and also reduces the thickness T T1 to a second thickness T T2 , and
after etching the substrate, performing a pull-back process to simultaneously reduce the thickness T T2 of the second pad layer of the top pad stack to a third thickness T T3 and the thickness of T B1 of the second pad layer of the bottom pad stack to a second thickness T B2 , wherein the pull-back process is a batch wet etch process and T T3 is different than T B2 ; and
performing a removal process to completely and simultaneously remove the second pad layers of the top and bottom pad stacks having reduced thickness from the substrate after forming the STI regions.
2. The method of claim 1 wherein the first pad layer comprises silicon oxide and the second pad layer comprises silicon nitride.
3. The method of claim 1 wherein the second pad layer is over the first pad layer.
4. The method of claim 1 wherein T T1 is about the same as T B1 .
5. The method of claim 1 wherein:
the thickness T T2 is reduced uniformly throughout the second pad layer of the top pad stack to the third thickness T T3 and the thickness T B1 is reduced uniformly throughout the second pad layer of the bottom pad stack to the second thickness T B2 by the pull-back process; and
the thickness T T3 is thinner than the thickness T B2 .
6. The method of claim 1 comprising:
forming a dielectric layer on the substrate covering the top pad stack and filling the trenches after performing the pull-back process;
reducing the thickness T B2 of the second pad layer of the bottom pad stack to a final thickness T B3 by a batch wet etch process after forming the dielectric layer, wherein the dielectric layer protects the top pad stack during reducing the thickness T B2 of the second pad layer to the final thickness T B3 , wherein T B3 is about the same as T T3 ; and
removing excess dielectric layer over the substrate to expose a top surface of the top pad stack.
7. The method of claim 6 wherein the second pad layers of the top and bottom pad stack having the thicknesses T T3 and T B3 are removed completely and simultaneously by a batch wet etch process after removing the excess dielectric layer.
8. The method of claim 6 wherein the dielectric layer comprises the same material as the first pad layer.
9. The method of claim 8 wherein the dielectric layer and the first pad layer comprises silicon oxide.
10. The method of claim 1 wherein the removal process comprises a batch wet etch process which removes the second pad layers using an etch solution which is highly selective to the first pad layer.
11. The method of claim 10 comprising forming a gate dielectric layer on the substrate, wherein the gate dielectric layer surrounds top, bottom and side surfaces of the substrate.
12. The method of claim 11 comprising:
forming a protective layer over a top surface of the gate dielectric layer, wherein the protective layer covers and protects portion of the gate dielectric layer which is disposed on and contact the top surface of the substrate; and
removing exposed portions of the gate dielectric layer which are disposed on and contact the bottom and side surfaces of the substrate and are not covered by the protective layer.
13. The method of claim 12 comprising:
removing the protective layer after removing exposed portions of the gate dielectric layer; and
patterning the remaining gate dielectric layer over the substrate using a patterned soft mask to form gate dielectric of transistors.
14. The method of claim 13 comprising forming a gate electrode layer on the substrate after patterning the remaining gate dielectric layer, wherein the gate electrode layer surrounds and directly contacts top, bottom and side surfaces of the substrate as well as covering the gate dielectric.
15. A method of forming a device comprising:
providing a substrate having top and bottom pad stacks, wherein each pad stack comprises at least first and second pad layers, and the second pad layers of the top and bottom pad stacks comprise an initial thickness T T1 and T B1 respectively;
forming shallow trench isolation (STI) regions in the substrate, wherein forming the STI regions comprises
patterning the top pad stack to form openings corresponding to the STI regions,
etching the substrate to form isolation trenches of the STI regions through the top pad stack openings, wherein etching the substrate removes exposed portions of the substrate and also reduces the thickness T T1 to a second thickness T T2 , and
after etching the substrate, performing a pull-back process to simultaneously reduce the thickness T T2 of the second pad layer of the top pad stack to a third thickness T T3 and the thickness of T B1 of the second pad layer of the bottom pad stack to a second thickness T B2 , wherein the pull-back process is a batch wet etch process and T T3 is different than T B2 ;
performing a removal process to completely and simultaneously remove the second pad layers of the top and bottom pad stacks having reduced thickness from the substrate after forming the STI regions;
forming a gate dielectric layer surrounding top, bottom and side surfaces of the substrate;
forming a protective layer over a top surface of the gate dielectric layer, wherein the protective layer only covers and protects portion of the gate dielectric layer which is disposed on and contacts the top surface of the substrate; and
removing exposed portions of the gate dielectric layer not covered by the protective layer.
16. The method of claim 15 wherein the second pad layers of the top and bottom pad stacks having reduced thickness are completely and simultaneously removed by a batch wet etch process.
17. The method of claim 16 wherein the batch wet process removes the second pad layers using an etch solution which is highly selective to the first pad layer.
18. The method of claim 15 wherein the first pad layer comprises silicon oxide and the second pad layer comprises silicon nitride.
19. The method of claim 15 wherein the protective layer comprises a photoresist layer.
20. The method of claim 15 wherein forming the STI regions further comprises:
forming a dielectric layer on the substrate covering the top pad stack and filling the trenches; and
reducing the thickness T B2 of the second pad layer of the bottom pad stack to a final thickness T B3 by a batch wet etch process after forming the dielectric layer, wherein the dielectric layer protects the top pad stack during reducing the thickness T B2 of the second pad layer of the bottom pad stack to the final thickness T B3 .