IP Library Granted Patent US 8,274,115
Granted Patent B2
US 8,274,115 · App. 12/050,956 · Granted Sep 25, 2012

Hybrid orientation substrate with stress layer

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Quick Facts
Patent No.
US 8,274,115
App. No.
12/050,956
Granted
Sep 25, 2012
Kind
B2
Abstract

A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.

Claims (31)

1. A method of fabricating a hybrid orientation substrate comprising the steps of:

providing a substrate comprising

a first region; the first region having a first surface layer having a first substrate orientation,

a second region; the second region having a second surface layer having a second substrate orientation, the first and second regions are electrically isolated by an isolation region,

the second surface layer comprising a plurality of sub-layers over the second region, wherein the plurality of sub-layers comprise an upper sub-layer comprising a semiconductor material having a second crystal orientation over a lower sub-layer comprising a first and a second pad buried layers sandwiching a stress layer having a neutral or moderate tensile stress; and

converting the stress layer to a high tensile stress layer, wherein converting the stress layer comprises subjecting the substrate to an ultra violet (UV) treatment.

2. The method of claim 1 wherein the first and second pad buried layers serve to improve adhesion between the stress layer and the substrate.

3. The method of claim 1 wherein the second pad buried layer serves as a buffer to avoid direct contact between the stress layer and the substrate.

4. A method of fabricating a hybrid orientation substrate comprising the steps of:

providing a substrate comprising

a first region; the first region having a first surface layer having a first substrate orientation,

a second region; the second region having a second surface layer having a second substrate orientation, the first and second regions are electrically isolated by an isolation region,

the second surface layer comprises a stress layer over the second region, wherein the stress layer is formed below a semiconductor material having a second crystal orientation and comprises a composite sub-layer having a plurality of buried layers, the stress layer having a neutral or moderate tensile stress; and

subjecting the substrate to an ultra violet (UV) treatment to convert the stress layer to a high tensile stress layer.

5. The method of claim 4 wherein the UV treatment is conducted at about 400-500° C. for about 10-15 mins.

6. The method of claim 4 wherein the plurality of buried layers comprise a first pad buried layer and a second pad buried layer sandwiching the stress layer.

7. The method of claim 6 wherein the second pad buried layer serves as a buffer to avoid direct contact between the stress layer and the substrate.

8. The method of claim 1 wherein the UV treatment is conducted at about 400-500° C. for about 10-15 mins.

9. A method of fabricating a hybrid orientation substrate comprising the steps of:

providing a surface substrate comprising

a first region having a first layer with a first substrate orientation,

a second region having a second layer with a second substrate orientation, the first and second regions are electrically isolated by an isolation region, wherein the second layer comprises a semiconductor material having a second crystal orientation formed over a stress layer comprising a composite layer having a plurality of buried layers, the stress layer having a neutral or moderate tensile stress over it;

bonding the surface substrate to a base substrate, wherein the base substrate has the same substrate orientation as the first layer; and

converting the stress layer of the second region to a high tensile stress layer, wherein converting the stress layer comprises subjecting the substrate to an ultra violet (UV) treatment.

10. The method of claim 9 wherein the stress layer comprises silicon nitride .

11. The method of claim 9 wherein the UV treatment is conducted at about 400-500° C. for about 10-15 mins.

12. The method of claim 9 wherein the second region comprises an upper or first sub-layer and a lower or second sub-layer.

13. The method of claim 12 wherein the lower or second sub-layer comprises the stress layer.

14. The method of claim 9 wherein the plurality of buried layers comprise a first pad buried layer and a second pad buried layer sandwiching the stress layer.

15. The method of claim 13 wherein the stress layer comprises a first stress which induces a second stress on the upper or first sub-layer.

16. The method of claim 15 wherein the stress layer comprises a tensile stress material which induces a compressive stress on the upper or first sub-layer.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2019
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: ALSEPHINA INNOVATIONS INC.
Reel/Frame 049669/0775 →
CHANGE OF NAME Recorded Aug 24, 2012
From: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
To: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
Reel/Frame 028842/0666 →
CHANGE OF NAME Recorded Aug 24, 2012
From: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 028842/0672 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2008
From: TEO, LEE WEE; LAI, CHUNG WOH; WIDODO, JOHNNY; TAN, SHYUE SENG; MISHRA, SHAILENDRA; LUN, ZHAO; LEE, YONG MENG; CHEE, JEFFREY
To: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
Reel/Frame 020956/0475 →