Integration of trench MOS with low voltage integrated circuits
View Patent ↗A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces, a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.
1. A method comprising:
forming a first trench in a substrate, the first trench having a first width;
forming a first oxide layer on side surfaces of the first trench;
forming a second trench in the substrate, below the first trench, the second trench having a second width less than the first width;
forming a second oxide layer on side and bottom surfaces of the second trench;
forming spacers on sides of the first and second trenches;
removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers;
filling the first and second trenches with a first poly-silicon to form a drain region;
removing the spacers, exposing side surfaces of the first poly-silicon;
forming a third oxide layer on the side surfaces and a top surface of the first poly-silicon; and
filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.
2. The method according to claim 1 , comprising:
doping the substrate around the second trench, after forming the second trench, to form a drift region.
3. The method according to claim 1 , comprising:
doping the substrate beneath the bottom surface of the second trench, after forming the spacers, to form a N + region.
4. The method according to claim 1 , comprising:
forming nitride spacers on the sides of the first trench after forming the first oxide layer; and
forming the second trench using the nitride spacers as a hard mask.
5. The method according to claim 1 , comprising:
forming a poly-silicon layer on the sides and bottom of the first and second trenches before forming the spacers.
6. The method according to claim 5 , comprising:
forming the third oxide layer and a fourth oxide layer on side surfaces of the first and second trenches by respectively oxidizing the first poly-silicon and the poly-silicon layer; and
removing the fourth oxide layer and the nitride spacers before filling the remainder with the second poly-silicon.
7. The method according to claim 6 , comprising:
forming a fifth oxide layer on the substrate after filling the remainder with the second poly-silicon; and
forming a low voltage transistor and/or a medium voltage transistor on the fifth oxide layer.
8. The method according to claim 1 , comprising:
forming the second oxide layer to be 500 Å to 20,000 Å in thickness; and
forming the third oxide layer to be 500 Å to 20,000 Å in thickness.