IP Library Granted Patent US 8,053,327
Granted Patent B2
US 8,053,327 · App. 11/614,961 · Granted Nov 8, 2011

Method of manufacture of an integrated circuit system with self-aligned isolation structures

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Quick Facts
Patent No.
US 8,053,327
App. No.
11/614,961
Granted
Nov 8, 2011
Kind
B2
Abstract

An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.

Claims (22)

1. A method of manufacture of an integrated circuit system comprising:

providing a substrate;

forming an isolation structure base in the substrate through a recess without removal of the substrate;

forming an epitaxial layer over the isolation structure base after annealing the substrate;

forming a trench through the epitaxial layer and into the substrate to the isolation structure base filled with isolation material; and

forming a first transistor in the substrate next to the isolation structure base.

2. The method as claimed in claim 1 further comprising forming a second transistor next to the isolation structure base and at an opposite side of the first transistor.

3. The method as claimed in claim 1 further comprising:

forming a self-aligned inverted T-shaped isolation structure with a gap fill of the trench.

4. The method as claimed in claim 1 further comprising growing the epitaxial layer over the substrate and the isolation structure base.

5. The method as claimed in claim 1 wherein forming the isolation structure base in the substrate includes annealing the isolation structure base to form a buried oxide.

6. A method of manufacture of an integrated integrated circuit system comprising:

providing a substrate;

forming an isolation structure base in the substrate through a recess without removal of the substrate;

forming an epitaxial layer over the isolation structure base after annealing the substrate;

forming a trench through the epitaxial layer and into the substrate to the isolation structure base;

forming a self-aligned inverted T-shaped isolation structure with a gap fill of the trench; and

forming a first transistor in the substrate next to the self-aligned inverted T-shaped isolation structure.

7. The method as claimed in claim 6 wherein forming the isolation structure base includes forming a buried oxide by implantation of oxygen.

8. The method as claimed in claim 6 wherein forming the trench through the epitaxial layer and into the substrate to the isolation structure base includes etching a self-aligned trench to the isolation structure base with a patterned mask.

9. The method as claimed in claim 6 wherein forming the self-aligned inverted T-shaped isolation structure with the gap fill of the trench includes forming an isolation structure column with a high density plasma oxide fill of the trench.

10. The method as claimed in claim 6 wherein forming the self-aligned inverted T-shaped isolation structure with the gap fill of the trench includes forming an isolation structure column in contact with a buried oxide.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2020
From: ALSEPHINA INNOVATIONS, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 053351/0839 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2019
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: ALSEPHINA INNOVATIONS INC.
Reel/Frame 049669/0775 →
CHANGE OF NAME Recorded Nov 20, 2018
From: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 047614/0081 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2007
From: MISHRA, SHAILENDRA; TEO, LEE WEE; LEE, YONG MENG; LUN, ZHAO; LAI, CHUNG WOH; TAN, SHYUE SENG; CHEE, JEFFREY; WIDODO, JOHNNY
To: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
Reel/Frame 018974/0677 →