Multiple layer resist scheme implementing etch recipe particular to each layer
View Patent ↗Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
1. A method of forming a metal line critical dimension in a single damascene process on a semiconductor substrate, the method comprising the steps of:
providing the semiconductor substrate including at least one metal level and at least one substrate dielectric layer thereover,
wherein the at least one substrate dielectric layer includes a hardmask layer over a hydrogenated silicon oxy-carbide (SiCOH) layer;
forming a multiple layer resist scheme including a first layer of a first type material over the substrate, a second layer of a second type material over the first layer, and a third layer of a third type material over the second layer,
wherein the first layer includes a planarizing layer, the second layer includes a dielectric layer, and the third layer includes a photoresist, and the first, second, and third types of materials alternate between organic and inorganic material;
patterning the third layer for the metal line critical dimension; and
sequentially etching to form the metal line critical dimension using a different tailored etch recipe for each of the first, second and third layer, and employing different process conditions for each etching.
2. The method of claim 1 , wherein the first and third type material includes organic materials, and the second type material includes inorganic material.
3. The method of claim 1 , wherein the first layer includes a near-frictionless carbon (NFC) material, the second layer includes an inorganic silicon dioxide material.
4. A method of forming a metal line critical dimension and a via critical dimension in a dual damascene process on a semiconductor substrate, the method comprising the steps of:
providing the semiconductor substrate including at least one metal level and at least one dielectric layer thereover,
wherein the at least one dielectric layer includes a hardmask layer over a
hydrogenated silicon oxy-carbide (SiCOH) layer;
forming a multiple layer resist scheme including a first layer of a first type material over the substrate, a second layer of a second type material over the first layer, and a third layer of a third type material over the second layer,
wherein the first layer includes a planarizing layer, the second layer includes a dielectric layer, and the third layer includes a photoresist, and wherein the first, second and third types of materials alternate between organic and inorganic material;
patterning the third layer for the metal line critical dimension and the via critical dimension; and
sequentially etching to form the metal line critical dimension and the via critical dimension using a different tailored etch recipe for each of the first, second and third layer.
5. The method of claim 4 , wherein the first and third type material include organic materials, and the second type material includes inorganic material.
6. The method of claim 4 , wherein the first layer includes a near-frictionless carbon (NFC) material, the second layer includes an inorganic silicon dioxide material.
7. A resist scheme for forming a wiring critical dimension in a single damascene process on a semiconductor substrate, the substrate including a metal level and at least one substrate dielectric layer thereover, the resist scheme comprising:
a first layer of a first type material over the substrate, the first layer including an organic planarizing layer, wherein the first layer includes a near-frictionless carbon (NFC) material;
a second layer of a second type material over the first layer, the second layer including an inorganic dielectric layer, wherein the inorganic dielectric layer includes one of: a low temperature oxide (LTO), silicon oxynitride (SiON), silicon nitride (Si 3 N 4 ), and silicon dioxide selected from the group consisting of thermal silicon dioxide, plasma-enhance chemical vapor deposited (PECVD) silicon dioxide and tetraethyl orthosilicate (Si(OC 2 H 5 ) 4 )(TEOS) silicon dioxide; and
a third layer of a third type material over the second layer, the third layer including an organic photoresist;
wherein the at least one substrate dielectric layer includes a hardmask layer including one of: tetraethyl orthosilicate (Si(OC 2 H 5 ) 4 ) silicon dioxide, silane oxide and thermal oxide, the hardmask layer provided over a hydrogenated silicon oxy-carbide (SiCOH) layer.