Integrated circuit with protected implantation profiles and method for the formation thereof
View Patent ↗A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.
1. A method for manufacturing an integrated circuit structure, comprising:
providing a semiconductor substrate;
forming an oxide-nitride-oxide dielectric layer on the semiconductor substrate;
forming a layer of polysilicon on the oxide-nitride-oxide dielectric layer;
forming a nitride hardmask layer on the layer of polysilicon;
patterning and forming a composite mask on the nitride hardinask;
etching the nitride hardmask, layer of polysilicon, oxide-nitride-oxide dielectric layer, and semiconductor substrate to form shallow trench isolation trenches;
filling the shallow trench isolation trenches with an oxide gap till;
polishing the oxide gap fill;
removing the nitride hardmask;
covering an array area over the semiconductor substrate with a photoresist mask;
removing the polysilicon and the oxide-nitride-oxide dielectric in a periphery area;
performing well and threshold implantation over the periphery area into the semiconductor substrate;
covering the periphery area over the semiconductor substrate with a photoresist mask; and
performing well and threshold implantation over the array area above the semiconductor substrate into the semiconductor substrate beneath the oxide-nitride-oxide
dielectric layer.
2. The method of claim 1 further comprising forming a channel implantation over the array area and the periphery area into the semiconductor substrate therebeneath.
3. The method of claim 2 further comprising:
forming a gate dielectric layer over at least portions of the periphery area;
forming at least one control gate layer over at least portions of the gate dielectric layer; and
forming an interlayer dielectric layer over at least portions of the array area and the periphery area.
4. The method of claim 3 further comprising forming at least one electrical contact through the interlayer dielectric layer to at least one portion of the control gate layer therebeneath, and at least one electrical contact through the interlayer dielectric layer to at least one portion of the polysilicon therebeneath.