Test structure for detecting via contact shorting in shallow trench isolation regions

1. A test structure for detecting void formation in semiconductor device layers, comprising:

a plurality of active device areas formed in a substrate;

a plurality of shallow trench isolation (STI) regions separating the active device areas;

a plurality of gate electrode structures formed across the active device areas and the STI regions; and

a matrix of vias formed over the active device areas and between the gate electrode structures;

wherein at least one edge of each of a pair of vias at opposite ends of a given one of the plurality of STI regions extends at least out to an edge of the associated active device area, wherein the matrix of vias is disposed so as to result in metal fill of a void formed within one of the STI regions, thereby resulting in a short between a pair of the vias disposed at opposite ends of the void.

2. The test structure of claim 1 , wherein the at least one edge of each of the pair of vias further extends beyond the edge of the associated active device area and into the given one of the STI regions.

3. The test structure of claim 1 , wherein opposite edges of each of the vias extend at least out to a corresponding edge of the associated active device area.

4. The test structure of claim 3 , wherein the opposite edges of each of The vias extends beyond the corresponding edges of the associated active device area and into an adjacent one of the STI regions.