IP Library › Granted Patent US 8,143,671

Granted Patent B2

US 8,143,671 · App. 12/640,192 · Granted Mar 27, 2012

Lateral trench FETs (field effect transistors)

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Quick Facts

Patent No.: US 8,143,671
App. No.: 12/640,192
Granted: Mar 27, 2012
Kind: B2

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Abstract

A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, and a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate. The first and second gate dielectric layers are sandwiched between and electrically insulate the semiconductor substrate from the first and second gate electrode regions, respectively. The first and second gate electrode regions are totally above and totally below, respectively, the top substrate surface.

Claims (36)

1. A semiconductor structure, comprising:

a semiconductor structure which includes a semiconductor substrate, wherein a top substrate surface of the semiconductor substrate defines a reference direction perpendicular to the top substrate surface;

a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, wherein the first doped transistor region is not a portion of a Source/Drain region of the first transistor, and wherein the first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity;

a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, wherein the second gate dielectric layer (i) is sandwiched between and (ii) electrically insulates the second gate electrode region and the semiconductor substrate;

a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, wherein the first gate dielectric layer (i) is sandwiched between and (ii) electrically insulates the first gate electrode region and the semiconductor substrate, wherein the first gate electrode region of the first transistor is on and totally above the top substrate surface, and wherein the second gate electrode region of the second transistor is on the semiconductor substrate and totally below the top substrate surface; and

a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate, wherein the second doped transistor region and the second doped Source/Drain portion comprise dopants of the first doping polarity, and wherein the second doped Source/Drain portion is in direct physical contact with the first doped Source/Drain portion.

2. The semiconductor structure of claim 1 , further comprising a third doped transistor region of the first transistor on the semiconductor substrate, wherein the third doped transistor region comprises dopants of a second doping polarity which is opposite to the first doping polarity.

3. The semiconductor structure of claim 1 , wherein the second gate dielectric layer surrounds the second gate electrode region.

4. The semiconductor structure of claim 3 , wherein the first doped Source/Drain portion is below the top substrate surface, and wherein the first doped Source/Drain portion is in direct physical contact with the second gate dielectric layer.

5. The semiconductor structure of claim 1 , wherein the second gate dielectric layer surrounds the second gate electrode region, wherein the first doped Source/Drain portion is below the top substrate surface, wherein the first doped Source/Drain portion is in direct physical contact with the second gate dielectric layer, and wherein the second doped Source/Drain portion is in direct physical contact with the second gate dielectric layer.

6. The semiconductor structure of claim 5 , wherein the second doped Source/Drain portion is disposed between the first doped Source/Drain portion and the top substrate surface.

7. The semiconductor structure of claim 1 , wherein the first doped transistor region of the first transistor has a first depth in the reference direction, wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction, and wherein the first depth is essentially equal to the second depth.

8. The semiconductor structure of claim 1 , wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction, wherein the second gate dielectric layer of the second transistor has a third depth in the reference direction, and wherein the third depth is greater than the second depth.

9. The semiconductor structure of claim 1 , further comprising, a shallow trench isolation (STI) region on the semiconductor substrate, wherein the STI region is in direct physical contact with the second gate dielectric layer and the second gate electrode region.

10. The semiconductor structure of claim 1 , wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction, wherein the second gate dielectric layer of the second transistor has a fourth depth in the reference direction, and wherein the fourth depth is less than the second depth.

11. A semiconductor structure, comprising:

a semiconductor structure which includes a semiconductor substrate, wherein the semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface;

a third doped transistor region of the first transistor on the semiconductor substrate, wherein the third doped transistor region comprises dopants of a second doping polarity which is opposite to the first doping polarity; and

a fourth doped transistor region of the first transistor and a fourth doped Source/Drain portion of the second transistor on the semiconductor substrate, wherein the fourth doped transistor region and the fourth doped Source/Drain portion comprise dopants of the first doping polarity, and wherein the fourth doped Source/Drain portion is in direct physical contact with the second doped Source/Drain portion.

12. The semiconductor structure of claim 11 , further comprising a fifth doped transistor region of the first transistor and a fifth doped Source/Drain portion of the second transistor on the semiconductor substrate, wherein the fifth doped transistor region and the fifth doped Source/Drain portion comprise dopants of the first doping polarity, and wherein the fifth doped Source/Drain portion is in direct physical contact with the fourth doped Source/Drain portion.

13. A semiconductor structure fabrication method, comprising:

providing a semiconductor structure which includes a semiconductor substrate, wherein a top substrate surface of the semiconductor substrate defines a reference direction perpendicular to the top substrate surface;

simultaneously forming a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, wherein the first doped transistor region is not a portion of a Source/Drain region of the first transistor, and wherein the first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity;

forming a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, wherein the second gate dielectric layer (i) is sandwiched between and (ii) electrically insulates the second gate electrode region and the semiconductor substrate;

forming a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, wherein the first gate dielectric layer (i) is sandwiched between and (ii) electrically insulates the first gate electrode region and the semiconductor substrate, wherein the first gate electrode region of the first transistor is on and totally above the top substrate surface, and wherein the second gate electrode region of the second transistor is on the semiconductor substrate and totally below the top substrate surface; and

simultaneously forming a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate, wherein the second doped transistor region and the second doped Source/Drain portion comprise dopants of the first doping polarity, and wherein the second doped Source/Drain portion is in direct physical contact with the first doped Source/Drain portion.

14. The method of claim 13 , wherein the first doped transistor region of the first transistor has a first depth in the reference direction, wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction, and wherein the first depth is essentially equal to the second depth.

15. The method of claim 13 , further comprising forming a third doped transistor region of the first transistor on the semiconductor substrate, wherein the third doped transistor region comprises dopants of a second doping polarity which is opposite to the first doping polarity.

16. The method of claim 13 , wherein said forming the second gate dielectric layer and the second gate electrode region is performed before said simultaneously forming the first doped transistor region and the first doped Source/Drain portion is performed.

17. The method of claim 16 , wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction, wherein the second gate dielectric layer of the second transistor has a third depth in the reference direction, and wherein the third depth is greater than the second depth.

18. The method of claim 13 , wherein said forming the second gate dielectric layer and the second gate electrode region is performed after said simultaneously forming the first doped transistor region and the first doped Source/Drain portion is performed.

19. The method of claim 18 , wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction, wherein the second gate dielectric layer of the second transistor has a fourth depth in the reference direction, and wherein the fourth depth is less than the second depth.

20. The method of claim 13 , wherein the second gate dielectric layer surrounds the second gate electrode region, wherein the first doped Source/Drain portion is below the top substrate surface, wherein the first doped Source/Drain portion is in direct physical contact with the second gate dielectric layer, and wherein the second doped Source/Drain portion is in direct physical contact with the second gate dielectric layer.

Assignments (5)

RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020

From: WILMINGTON TRUST, NATIONAL ASSOCIATION

To: GLOBALFOUNDRIES INC.

Reel/Frame 054636/0001 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2020

From: ALSEPHINA INNOVATIONS, INC.

To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Reel/Frame 053351/0839 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2019

From: GLOBALFOUNDRIES INC.

To: ALSEPHINA INNOVATIONS INC.