Performance enhancement in transistors comprising high-K metal gate stack by reducing a width of offset spacers

1. A method of forming a transistor, the method comprising:

performing a first deposition process to form a first sub-layer of a spacer layer above an active region and a gate electrode structure formed on said active region, said gate electrode structure comprising a high-k dielectric material and a dielectric cap material formed on an electrode material, wherein forming said first sub-layer comprises providing a first precursor so as to form a preform of said first sub-layer and subsequently providing a second precursor to form at least a portion of said first sub-layer;

performing a second deposition process to form a second sub-layer of said spacer layer on said first sub-layer;

forming a spacer from said spacer layer;

replacing a portion of said active region with a strain-inducing semiconductor material by using said spacer and said dielectric cap material as a mask;

removing said spacer and said dielectric cap material; and

forming drain and source regions in said active region.

2. The method of claim 1 , wherein said first deposition process is performed at a first process temperature that is less than a second process temperature used in said second deposition process.

3. The method of claim 2 , wherein said first process temperature is 550° C. or less.

4. The method of claim 3 , wherein said second process temperature is 700° C. or higher.

5. The method of claim 1 , further comprising performing an anneal process on at least one of said spacer layer and said spacer prior to replacing a portion of said active region with a strain-inducing semiconductor material.

6. The method of claim 1 , wherein said first sub-layer is formed with a thickness of 0.2-3 nm.

7. The method of claim 6 , wherein said second sub-layer is formed with a thickness of 2-5 nm.

8. The method of claim 1 , wherein said first and second sub-layers comprise silicon and nitrogen.

9. The method of claim 1 , wherein said first and second sub-layers are formed in the same process reactor without exposure to the ambient atmosphere.

10. The method of claim 1 , further comprising forming a protective spacer structure on sidewalls of said gate electrode structure prior to forming said spacer layer.

11. The method of claim 10 , wherein forming a protective spacer structure comprises forming a silicon nitride spacer on sidewalls of said gate electrode structure and forming a silicon dioxide spacer on said silicon nitride spacer.

12. The method of claim 10 , wherein removing said spacer and said dielectric cap material comprises performing an etch process and using at least a portion of said protective spacer structure as an etch stop.

13. A method, comprising:

performing a deposition sequence on the basis of at least two different process parameter settings so as to form a spacer layer above a first active region of a first transistor and a second active region of a second transistor, said spacer layer covering a first gate electrode structure formed on a portion of said first active region, said spacer layer covering a second gate electrode structure formed on a portion of said second active region, said first and second transistors differing in conductivity type, wherein said deposition sequence comprises a deposition process based on two different precursors that are to be sequentially supplied to a deposition reactor;

forming a spacer element selectively on sidewalls of said first gate electrode structure from said spacer layer and preserving said spacer layer above said second active region;

forming a strain-inducing semiconductor material in said first active region by using said spacer element and said spacer layer as a mask;

removing said spacer element and said spacer layer; and

forming drain and source regions in said first and second active regions.

14. The method of claim 13 , wherein said deposition sequence further comprises a thermally activated deposition process based on a single gas ambient established in said deposition reactor.

15. The method of claim 13 , further comprising forming a protective spacer element on sidewalls of said first and second gate electrode structures prior to performing said deposition sequence.

16. The method of claim 13 , wherein said spacer layer is formed with a thickness of 8 nm or less.

17. A method of forming a semiconductor device, the method comprising:

forming a protective spacer element on sidewalls of a gate electrode structure formed on a semiconductor region;

forming a sacrificial spacer element on said protective spacer element;

performing a deposition sequence so as to deposit a spacer layer above said gate electrode comprising said protective spacer element and said sacrificial spacer element, said deposition sequence including a multi-step deposition process and a low pressure chemical vapor deposition process;

forming a spacer element from said spacer layer;

forming a strain-inducing semiconductor material in said active region;

removing said spacer element;

forming a sidewall spacer structure after removing said spacer element; and

forming drain and source regions in said semiconductor region by using said sidewall spacer structure as an implantation mask.

18. The method of claim 17 , wherein said spacer layer is formed with a thickness of 8 nm or less.