Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability
View Patent ↗Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.
1. A method of simultaneously forming different structures in an integrated circuit structure, said method comprising:
forming a release layer on a dielectric layer, having a top surface;
etching an opening extending through said release layer and into said dielectric layer such that, within said dielectric layer, said opening has a deep first portion and a shallow second portion above and wider than said deep first portion and further such that edges of said release layer at said opening extend laterally over said shallow second portion, said etching comprising isotropically etching said dielectric layer to form said shallow second portion;
lining said opening with a liner;
filling said opening with a conductor, said lining and said filling resulting in a conductive interconnect line in said shallow second portion and a conductive via in said deep first portion, said conductive interconnect line having lined corners adjacent said top surface of said dielectric layer;
polishing said liner and said conductor off of said release layer; and
removing said release layer using a process other than chemical mechanical processing such that any trace amounts of said liner and said conductor that remain on said release layer after said polishing are completely removed as said release layer is removed.
2. The method of claim 1 , further comprising:
after said polishing of said liner and said conductor off of said release layer and before said removing of said release layer, recessing said conductive interconnect line level with said top surface of said dielectric layer; and
after said removing of said release layer, depositing a capping layer over said dielectric layer and said conductor.
3. The method of claim 1 ,
said removing of said release layer resulting in a narrow top portion of said conductive interconnect line that extends above said dielectric layer, and
said method further comprising:
depositing a second dielectric layer over said dielectric layer and said conductive interconnect line such that said second dielectric layer laterally surrounds said narrow top portion of said conductive interconnect line;
polishing said second dielectric layer to expose said narrow top portion of said conductive interconnect line; and
depositing a capping layer over said second dielectric layer and said narrow top portion of said conductive interconnect line.
4. The method of claim 1 ,
said forming of said release layer comprising depositing an organic material, and
said removing of said release layer comprising dissolving said release layer in an organic solvent.
5. The method of claim 1 ,
said forming of said release layer comprising depositing a dielectric material, and
said removing of said release layer comprising performing a wet etching process.
6. The method of claim 1 ,
said forming of said release layer comprising depositing one of a metal and a metal nitride, and
said removing of said release layer comprising performing a wet etching process.
7. The method of claim 1 , said removing of said release layer comprising selectively removing said release layer to prevent etch back of at least one of said dielectric layer and said conductive interconnect line.
8. The method of claim 1 , further comprising, after said removing of said release layer, polishing said dielectric layer and said conductive interconnect line level to adjust for any etch back of said dielectric layer and said conductive interconnect line.
9. A method of simultaneously forming different structures in an integrated circuit structure, said method comprising:
forming a release layer on a dielectric layer, having a top surface, by depositing an organic material;
etching an opening extending through said release layer and into said dielectric layer such that, within said dielectric layer, said opening has a deep first portion and a shallow second portion above and wider than said deep first portion and further such that edges of said release layer at said opening extend laterally over said shallow second portion, said etching comprising isotropically etching said dielectric layer to form said shallow second portion;
lining said opening with a liner;
filling said opening with a conductor, said lining and said filling resulting in a conductive interconnect line in said shallow second portion and a conductive via in said deep first portion, said conductive interconnect line having lined corners adjacent said top surface of said dielectric layer;
polishing said liner and said conductor off of said release layer; and
removing said release layer by dissolving said release layer in an organic solvent such that any trace amounts of said liner and said conductor that remain on said release layer after said polishing are completely removed as said release layer is removed.
10. The method of claim 9 , further comprising:
after said polishing of said liner and said conductor off of said release layer and before said removing of said release layer, recessing said conductive interconnect line level with said top surface of said dielectric layer; and
after said removing of said release layer, depositing a capping layer over said dielectric layer and said conductor.
11. The method of claim 9 ,
said removing of said release layer resulting in a narrow top portion of said conductive interconnect line that extends above said dielectric layer, and
said method further comprising:
depositing a second dielectric layer over said dielectric layer and said conductive interconnect line such that said second dielectric layer laterally surrounds said narrow top portion of said conductive interconnect line forming reinforced corners;
polishing said second dielectric layer to expose said narrow top portion of said conductive interconnect line; and
depositing a capping layer over said second dielectric layer and said narrow top portion of said conductive interconnect line.
12. The method of claim 9 , said removing of said release layer comprising selectively removing said release layer to prevent etch back of at least one of said dielectric layer and said conductive interconnect line.
13. The method of claim 9 , further comprising, after said removing of said release layer, polishing said dielectric layer and said conductive interconnect line level to adjust for any etch back of said dielectric layer and said conductive interconnect line.
14. A method of simultaneously forming different structures in an integrated circuit structure, said method comprising:
forming a release layer on a dielectric layer, having a top surface, by depositing a dielectric material;
etching an opening extending through said release layer and into said dielectric layer such that, within said dielectric layer, said opening has a deep first portion and a shallow second portion above and wider than said deep first portion and further such that edges of said release layer at said opening extend laterally over said shallow second portion, said etching comprising isotropically etching said dielectric layer to form said shallow second portion;
lining said opening with a liner;
filling said opening with a conductor, said lining and said filling resulting in a conductive interconnect line in said shallow second portion and a conductive via in said deep first portion, said conductive interconnect line having lined corners adjacent said top surface of said dielectric layer;
polishing said liner and said conductor off of said release layer; and
removing said release layer by performing a wet etch process such that any trace amounts of said liner and said conductor that remain on said release layer after said polishing are completely removed as said release layer is removed.
15. The method of claim 14 , further comprising:
after said polishing of said liner and said conductor off of said release layer and before said removing of said release layer, recessing said conductive interconnect line level with said top surface of said dielectric layer; and
after said removing of said release layer, depositing a capping layer over said dielectric layer and said conductor.
16. The method of claim 14 ,
said removing of said release layer resulting in a narrow top portion of said conductive interconnect line that extends above said dielectric layer and said method further comprising:
depositing a second dielectric layer over said dielectric layer and said conductive interconnect line such that said second dielectric layer laterally surrounds said narrow top portion of said conductive interconnect line forming reinforced corners;
polishing said second dielectric layer to expose said narrow top portion of said conductive interconnect line; and
depositing a capping layer over said second dielectric layer and said narrow top portion of said conductive interconnect line.
17. The method of claim 14 , said removing of said release layer comprising selectively removing said release layer to prevent etch back of at least one of said dielectric layer and said conductive interconnect line.
18. The method of claim 14 , further comprising, after said removing of said release layer, polishing said dielectric layer and said conductive interconnect line level to adjust for any etch back of said dielectric layer and said conductive interconnect line.
19. A method of simultaneously forming different structures in an integrated circuit structure, said method comprising:
forming a release layer on a dielectric layer, having a top surface, by depositing one of a metal and a metal nitride material;
etching an opening extending through said release layer and into said dielectric layer such that, within said dielectric layer, said opening has a deep first portion and a shallow second portion above and wider than said deep first portion and further such that edges of said release layer at said opening extend laterally over said shallow second portion, said etching comprising isotropically etching said dielectric layer to form said shallow second portion;
lining said opening with a liner;
filling said opening with a conductor, said lining and said filling resulting in a conductive interconnect line in said shallow second portion and a conductive via in said deep first portion, said conductive interconnect line having lined corners adjacent said top surface of said dielectric layer;
polishing said liner and said conductor off of said release layer; and
removing said release layer by performing a wet etch process that selectively removes said release layer such that etch back of at least one of said dielectric layer and said conductive interconnect line is prevented and such that any trace amounts of said liner and said conductor that remain on said release layer after said polishing are completely removed.
20. The method of claim 19 , further comprising:
after said polishing of said liner and said conductor off of said release layer and before said removing of said release layer, recessing said conductive interconnect line level with said top surface of said dielectric layer; and
after said removing of said release layer, depositing a capping layer over said dielectric layer and said conductor.
21. The method of claim 19 ,
said removing of said release layer resulting in a narrow top portion of said conductive interconnect line that extends above said dielectric layer and said method further comprising:
depositing a second dielectric layer over said dielectric layer and said conductive interconnect line such that said second dielectric layer laterally surrounds said narrow top portion of said conductive interconnect line forming reinforced corners;
polishing said second dielectric layer to expose said narrow top portion of said conductive interconnect line; and
depositing a capping layer over said second dielectric layer and said narrow top portion of said conductive interconnect line.