Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach
View Patent ↗By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches.
1. A method, comprising:
forming a first stress-inducing dielectric layer above a P-channel transistor and an N-channel transistor;
selectively removing a portion of said first stress-inducing layer from above said P-channel transistor;
forming a second stress-inducing dielectric layer above said P-channel transistor and said N-channel transistor;
selectively removing a portion of said second stress-inducing layer from above said N-channel transistor;
forming a dielectric buffer layer above said first stress-inducing dielectric layer by a non-plasma assisted first deposition process prior to selectively removing said portion of said first stress-inducing layer from above said P-channel transistor;
forming an etch control layer on said first stress inducing layer prior to forming said second stress inducing layer, and wherein selectively removing said portion of the second stress inducing layer comprises performing an etch process and using said etch control layer to determine an endpoint of said etch process; and
depositing an interlayer dielectric material by performing a plasma enhanced chemical vapor deposition process.
2. The method of claim 1 , wherein said first stress-inducing layer is a tensile-stressed layer and is formed prior to forming said second stress-inducing layer.
3. The method of claim 2 , further comprising forming an etch stop layer above said P-channel transistor and said N-channel transistor prior to forming said first stress-inducing layer.
4. The method of claim 1 , wherein performing said non-plasma assisted deposition process comprises performing a thermally activated chemical vapor deposition process.
5. The method of claim 4 , wherein said thermally activated chemical vapor deposition process is performed on the basis of TEOS (tetra ethyl orthosilicate) to deposit silicon dioxide.
6. The method of claim 1 , wherein performing said non-plasma assisted deposition process comprises applying said dielectric buffer layer by spin coating.
7. The method of claim 1 , further comprising forming a contact opening in the interlayer dielectric layer using at least one of said first or second stress-inducing layers and said dielectric buffer layer as etch stop materials.