Method of fabricating hetero-junction bipolar transistor (HBT)
View Patent ↗A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>.
1. A method of fabricating a hetero-junction bipolar transistor, the method comprising:
providing a substrate including a bulk silicon having a <110> crystalline orientation;
forming a buried oxide (BOX) within the bulk silicon having the <110> crystalline orientation;
forming a silicon-on-insulator (SOI) region over the BOX, where the SOI region has a <100> crystalline orientation;
forming a pnp hetero-junction bipolar structure on the bulk silicon having the <110> crystalline orientation, the pnp hetero-junction bipolar structure including;
an emitter, a base and a collector, wherein the emitter is formed over the base, wherein the base is formed over the collector, and the collector is disposed on the bulk silicon having the <110> crystalline orientation; and
forming a npn hetero-junction bipolar transistor (HBT) on the SOI region, the npn HBT including:
an npn collector disposed on the SOI region;
an npn base disposed on the collector to form a hetero-junction therebetween;
and
an npn emitter disposed on the base to form a hetero-junction therebetween.
2. The method according to claim 1 , further comprising forming a shallow trench isolation (STI) region in each of the bulk silicon having the <110> crystalline orientation and the SOI region.
3. The method according to claim 1 , further comprising forming a deep trench in each of the bulk silicon having the <110> crystalline orientation and the SOI region.
4. The method of claim 1 , wherein the bulk silicon having the <110> crystalline orientation of the substrate is a handle wafer and the SOI region is disposed at least partially on the handle wafer.
5. The method of claim 4 , wherein the npn HBT is disposed over the SOI region.
6. A method of fabricating a hetero-junction bipolar transistor (HBT), the method comprising:
providing a substrate including a bulk silicon having a <110> crystalline orientation;
forming a buried oxide (BOX) within the bulk silicon having the <110> crystalline orientation;
forming a silicon-on-insulator (SOI) region over the BOX, where the SOI region has a <100> crystalline orientation;
forming at least one hetero-junction bipolar structure over the substrate, the at least one hetero-junction bipolar structure being a pnp structure disposed on the bulk silicon having the <110> crystalline orientation,
wherein the pnp structure includes an emitter, a base and a collector,
wherein the emitter is formed on the base to form a hetero-junction therebetween,
wherein the base is formed on the collector to form a hetero-junction therebetween, and
wherein the collector is disposed on the substrate.
7. The method of claim 6 , wherein the substrate further comprises a region including a combination of the <100> crystalline orientation and the <110> crystalline orientation.
8. The method of claim 7 , wherein the at least one hetero-junction bipolar structure further includes a second hetero-junction bipolar structure being an npn structure disposed on the bulk silicon of <100> crystalline orientation.
9. The method of claim 6 , wherein the bulk silicon of <100> crystalline orientation is incorporated in the silicon-on-insulator (SOI) region of the substrate.
10. The method of claim 6 , wherein the bulk silicon of <100> crystalline orientation is a handle wafer.
11. The method of claim 6 , wherein the substrate includes at least one of a shallow-trench-isolation (STI) region and a deep trench.