Metal gate stack and semiconductor gate stack for CMOS devices
View Patent ↗A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.
1. A semiconductor structure comprising:
a high-k material metal gate structure to an n-type semiconductor device, and a semiconductor gate structure to a p-type semiconductor device, wherein said high-k material metal gate structure includes:
a high dielectric constant (high-k) material portion having a dielectric constant greater than 8.0 and located on a semiconductor substrate;
a metal gate portion comprising a metal having a composition to provide a threshold voltage for an n-type semiconductor device, said metal gate portion vertically abutting said high-k material portion;
an oxygen-impermeable dielectric spacer laterally abutting sidewalls of said high-k material portion and said metal gate portion; and
a first low-k spacer comprising a dielectric material having a dielectric constant less than 4.0 and laterally contacting sidewalls of said oxygen-impermeable dielectric spacer, wherein said first low-k spacer is laterally spaced from said high-k material portion and said metal gate portion by said oxygen-impermeable dielectric spacer;
and wherein said semiconductor gate structure includes:
a semiconductor oxide containing gate dielectric portion having a dielectric constant less than 8.0 and located directly on said semiconductor substrate;
a doped semiconductor portion comprising a doped semiconductor material and vertically abutting said gate dielectric; and
a second low-k gate spacer comprising said dielectric material and laterally abutting sidewalls of said semiconductor oxide containing gate dielectric portion and said doped semiconductor portion, wherein said oxygen-impermeable dielectric spacer is not present between the second low-k gate spacer and the sidewalls of the doped semiconductor portion.
2. The semiconductor structure of claim 1 , wherein said high-k material portion further includes a chemical oxide portion vertically abutting said high-k material portion and said semiconductor substrate and comprising an oxide of a semiconductor material of said semiconductor substrate.
3. The semiconductor structure of claim 1 , wherein said oxygen-impermeable dielectric spacer has an L-shaped vertical cross-sectional area and vertically abuts said semiconductor substrate.
4. The semiconductor structure of claim 1 , wherein said oxygen-impermeable dielectric spacer comprises silicon nitride.
5. The semiconductor structure of claim 1 , wherein said low-k gate spacer comprises silicon oxide.
6. The semiconductor structure of claim 1 , wherein said low-k gate spacer comprises a low-k dielectric material having a dielectric constant less than 2.8.
7. The semiconductor structure of claim 1 , wherein said high-k material portion comprises one of HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, and an alloy thereof, wherein each value of x is independently from about 0.5 to about 3 and each value of y is independently from 0 to about 2.
8. The semiconductor structure of claim 1 , wherein said metal gate portion comprises one of TiN, ZrN, HfN, VN, NbN, TaN, WN, TiAlN, TaCN, W, Ta, Ti, other conductive refractory metal nitrides, and an alloy thereof.
9. The semiconductor structure of claim 1 , wherein said high-k material metal gate structure further includes a second doped semiconductor portion comprising a doped semiconductor and vertically abutting said metal gate portion.
10. The semiconductor structure of claim 9 , wherein said semiconductor gate structure further includes a third doped semiconductor portion comprising said doped semiconductor and vertically abutting said doped semiconductor portion.
11. The semiconductor structure of claim 10 , wherein said third doped semiconductor portion and said doped semiconductor portion comprise different materials.
12. A semiconductor structure comprising:
a high-k material metal gate structure to an n-type semiconductor device, and a semiconductor gate structure to a p-type semiconductor device, wherein said high-k material metal gate structure includes:
a high dielectric constant (high-k) material portion having a dielectric constant greater than 8.0 and located on a semiconductor substrate;
a metal gate portion comprising a metal having a composition to provide a threshold voltage for an n-type semiconductor device, said metal gate portion vertically abutting said high-k material portion;
a first doped semiconductor portion vertically abutting the metal gate portion;
an oxygen-impermeable dielectric spacer laterally abutting sidewalls of said high-k material portion and said metal gate portion; and
a first low-k spacer comprising a dielectric material having a dielectric constant less than 4.0 and laterally contacting sidewalls of said oxygen-impermeable dielectric spacer, wherein said first low-k spacer is laterally spaced from said high-k material portion and said metal gate portion by said oxygen-impermeable dielectric spacer;
and wherein said semiconductor gate structure includes:
a semiconductor oxide containing gate dielectric portion having a dielectric constant less than a dielectric constant of silicon oxynitride and located directly on said semiconductor substrate;
a second doped semiconductor portion comprising a doped semiconductor material and vertically abutting said gate dielectric;
a third doped semiconductor portion vertically abutting the second doped semiconductor portion, wherein the third doped semiconductor portion of the semiconductor gate structure and the first doped semiconductor portion of the high-k material metal gate structure have an identical composition; and
a second low-k gate spacer comprising said dielectric material and laterally abutting sidewalls of said semiconductor oxide containing gate dielectric portion and said second and third doped semiconductor portion, wherein said oxygen-impermeable dielectric spacer is not present between the second low-k gate spacer and the sidewalls of the doped semiconductor portion.