Selective silicon-on-insulator isolation structure and method
View Patent ↗A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
1. A semiconductor device comprising:
a semiconductor substrate having a top surface;
a first region of said substrate having a first well extending into said semiconductor substrate from said top surface of said substrate and bounded in a direction perpendicular to said top surface by a first trench isolation, said first trench isolation extending perpendicular to said top surface of said substrate into said substrate, said first well abutting said semiconductor substrate;
a source and a drain of a first FET formed in said first well of said first region, said source and said drain abutting different sidewall regions of said first trench isolation;
a second region of said substrate having a second well extending into said semiconductor substrate from said top surface and bounded in a direction perpendicular to said top surface by a second trench isolation, said second trench isolation having a vertical portion extending perpendicular to said top surface into said substrate and a lateral portion extending from said vertical portion in a direction parallel to said top surface of said substrate, said second well abutting said semiconductor substrate; and
a source and a drain of a second FET formed in said well of said second region, said source of said second FET abutting a first region of said vertical portion and an abutting first region of said lateral portion, said drain of said second FET abutting a second region of said vertical portion and an abutting second region of said lateral portion, said source and said drain of said second FET intervening between said lateral portion and said top surface of said substrate.
2. The semiconductor device of claim 1 , wherein a vertical edge of said lateral portion of said second trench isolation is aligned to an outer edge of a spacer formed on a sidewall of a gate electrode of said second FET.
3. The semiconductor device of claim 1 further including a buried oxide layer in said substrate below said first and second trench isolations.
4. The semiconductor device of claim 1 , wherein said lateral portion of said second trench isolation has an upper region consisting of a first dielectric material and a lower region consisting of a second dielectric material, said first and second dielectric materials different from each other.
5. The semiconductor device of claim 4 , wherein said first dielectric material is high-density plasma (DHP) oxide or spin-on-glass and said second dielectric material is tetraethoxysilane (TEOS) chemical-vapor-deposition (CVD) oxide or spin on glass.
6. The semiconductor device of claim 4 , wherein said vertical portion of said second trench isolation is comprised of a third dielectric material, said third dielectric material different from said first or said second dielectric material, said first, second and third materials in separate layers.
7. The semiconductor device of claim 6 , wherein said third dielectric material is high-density plasma (DHP) oxide.
8. The semiconductor device of claim 4 , wherein said first dielectric material is high-density plasma (DHP) oxide and said second dielectric material is tetraethoxysilane (TEOS) chemical-vapor-deposition (CVD) oxide.
9. The semiconductor device of claim 4 , wherein said vertical portion of said second trench isolation is comprised of a third dielectric material, said third dielectric material different from both said first and second dielectric material.
10. The semiconductor device of claim 1 , further including:
a conformal dielectric liner formed on all surfaces of said second trench isolation that abut said substrate.
11. The semiconductor device of claim 10 , wherein said liner is comprised of silicon dioxide or silicon nitride.
12. The semiconductor device of claim 1 , wherein:
an upper region of said vertical portion of said second trench isolation is integral with an upper region of said lateral portion of said second trench isolation and is comprised of a first dielectric material,
a lower region of said vertical portion of said second trench isolation is integral with a lower region of said lateral portion of said second trench isolation and is comprised of a second dielectric material, said lower region of said lateral portion of said second trench isolation extending completely under said upper region of said lateral portion of said second trench isolation, and
said lower region of said vertical portion of said second trench isolation extends past said lateral portion of said second trench isolation into said substrate.
13. The semiconductor device of claim 1 , wherein a vertical edge of said lateral portion of said second trench isolation is aligned between an outer edge of a spacer formed on a sidewall of a gate electrode of said second FET and an inner edge of said spacer abutting said sidewall of said gate electrode.
14. The semiconductor device of claim 1 , wherein a vertical edge of said lateral portion of said second trench isolation is aligned to said sidewall of a gate electrode of said second FET.
15. The structure of claim 1 , wherein said first well extends under said first trench isolation and said second well extends under said second trench isolation.
16. The structure of claim 1 , wherein said first well extends under said first trench isolation and said second well extends under only said lateral portion of said second trench isolation.
17. The structure of claim 1 , wherein a vertical edge of said lateral portion of said second trench isolation is aligned between two opposite sides of said gate electrode.