Methods of forming and programming an electronically programmable resistor

1. A method comprising:

forming a diffusion resistor in a substrate, the diffusion resistor including a single doped body,

wherein the substrate includes a p-type doped substrate region and wherein the single doped body is doped n-type during the forming;

forming a trapped charge region adjacent to and in direct contact with the single doped body, the forming of the trapped charge region including forming the trapped charge region such that the single doped body is substantially parallel with the trapped charge region and the single doped body substantially separates the trapped charge region from the substrate; and

adjusting a resistance of the diffusion resistor by controlling a trapped charge in the trapped charge region by varying an amount of trapped charge in the trapped charge region.

2. The method of claim 1 , wherein the trapped charge region forming includes forming a pair of silicon oxide layers having a silicon nitride layer therebetween, wherein the trapped charge is located within the silicon nitride layer.

3. The method of claim 2 , further comprising forming a gate layer over an upper one of the silicon oxide layers, and patterning the gate layer, the pair of silicon oxide layers and the silicon nitride layers into a gate structure.

4. The method of claim 1 , wherein the trapped charge region forming includes forming a trapped charge layer including at least one of silicon nitride and silicon oxide.

5. The method of claim 1 , wherein the trapped charge region forming includes forming a polysilicon layer, wherein the trapped charge is located within the polysilicon layer.

6. The method of claim 1 , wherein the forming includes setting the resistance at a value lower than a target resistance to be achieved by the adjusting.

7. The method of claim 1 , wherein the substrate includes an n-type isolation below the trapped charge region, and wherein the trapped charge region forming includes applying a forward bias across the p-type doped substrate region to the n-type isolation and a reverse bias across the p-type doped substrate region to the diffusion resistor to accelerate the electrons into the trapped charge region.

8. The method of claim 1 , wherein the trapped charge region forming includes applying a reverse bias across the p-type doped substrate region to the diffusion resistor to accelerate electrons into the trapped charge region.

9. The method of claim 8 , wherein the substrate includes an n-type isolation below the trapped charge region, and wherein the trapped charge region forming further includes applying a forward bias across the p-type doped substrate region to the n-type isolation to provide electrons for acceleration into the trapped charge region.

10. A method comprising:

forming a diffusion resistor in a substrate, the diffusion resistor including a single doped body, the substrate including a p-type doped substrate region and the single doped body being doped n-type;

forming a trapped charge region adjacent to and in direct contact with the single doped body such that the single doped body is substantially parallel with the trapped charge region, the single doped body being formed to substantially separate the trapped charge region from the substrate; and

electrically programming a resistance of the diffusion resistor by controlling an amount of trapped charge in the trapped charge region.

11. The method of claim 10 , wherein the trapped charged region includes a pair of silicon oxide layers having a silicon nitride layer therebetween, wherein the trapped charge is located within the silicon nitride layer.

12. The method of claim 11 , further comprising forming a gate layer over an upper one of the silicon oxide layers, and patterning the gate layer, the pair of silicon oxide layers and the silicon nitride layers into a gate structure.

13. The method of claim 10 , further comprising forming the trapped charge region by forming a trapped charge layer including at least one of silicon nitride and silicon oxide.

14. The method of claim 10 , further comprising forming the trapped charge region by forming a polysilicon layer, wherein the trapped charge is located within the polysilicon layer.

15. The method of claim 10 , wherein the forming includes setting the resistance at a value lower than a target resistance to be achieved by the programming.

16. The method of claim 10 , further comprising forming the trapped charge region by applying a reverse bias across the p-type doped substrate region to the diffusion resistor to accelerate electrons into the trapped charge region.

17. The method of claim 16 , wherein the substrate includes an n-type isolation below the trapped charge region, and wherein the trapped charge region forming further includes applying a forward bias across the p-type doped substrate region to the n-type isolation to provide electrons for acceleration into the trapped charge region.

18. The method of claim 1 , wherein single doped body is permanently doped independent of the amount of trapped charge in the trapped charge region.

19. The method of claim 10 , wherein single doped body is permanently doped independent of the amount of trapped charge in the trapped charge region.