IP Library Granted Patent US 7,504,311
Granted Patent B2
US 7,504,311 · App. 11/762,376 · Granted Mar 17, 2009

Structure and method of integrating compound and elemental semiconductors for high-performance CMOS

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Quick Facts
Patent No.
US 7,504,311
App. No.
11/762,376
Granted
Mar 17, 2009
Kind
B2
Abstract

A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

Claims (11)

1. A method for fabricating a semiconductor substrate, comprising the steps of:

epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate;

depositing an insulating layer on top of the elemental semiconductor layer, so as to form a first substrate;

wafer bonding the first substrate onto a monocrystalline substrate, such that the insulating layer bonds with the monocrystalline substrate; and

removing a portion of the compound semiconductor substrate wherein an etch stop layer is formed between portions of the compound semiconductor substrate and etching the compound semiconductor substrate to the etch stop layer.

2. The method as recited in claim 1 wherein the step of removing includes employing a splitting method to separate the portion of the compound semiconductor substrate.

3. The method as recited in claim 1 , wherein the insulating layer is deposited on the monocrystalline substrate, the elemental semiconductor, or both.

4. The method as recited in claim 1 , wherein said elemental semiconductor is substantially lattice-matched to the compound semiconductor substrate.

5. The method as recited in claim 1 , wherein the elemental semiconductor includes elemental Ge.

6. The method as recited in claim 1 , wherein the compound semiconductor includes at least one of GaAs, AlGaAs, GaP, AlGaP and InGaAs.

7. The method as recited in claim 1 , wherein the monocrystalline substrate includes a silicon substrate.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2020
From: ALSEPHINA INNOVATIONS, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 053351/0839 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2019
From: GLOBALFOUNDRIES INC.
To: ALSEPHINA INNOVATIONS INC.
Reel/Frame 049709/0871 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →