Deep trench semiconductor structure and method
View Patent ↗An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.
1. An electrical structure comprising:
a semiconductor substrate comprising a deep trench;
a shallow trench isolation layer formed over said semiconductor substrate;
an oxide liner layer formed over an exterior surface of said deep trench;
a first field effect transistor (FET) formed within said semiconductor substrate, wherein said first FET comprises a first source structure, a first drain structure, and a first gate structure, wherein said first gate structure comprises a first gate contact connected to a first polysilicon fill structure, wherein said first gate contact extends through said shallow trench isolation layer and through a top surface of said first polysilicon fill structure, wherein said first polysilicon fill structure is formed over said oxide liner layer and within said deep trench, wherein said first polysilicon fill structure is configured to flow current laterally across said first polysilicon fill structure such that said current will flow parallel to a top surface of said semiconductor substrate;
a first P tub formed within said semiconductor substrate and below said shallow trench isolation layer, wherein said shallow trench isolation layer comprises a first opening, wherein said first source structure extends from a top surface of said shallow trench isolation layer into a first portion of said first opening, wherein a first portion of said first P tub extends from a bottom surface of said shallow trench isolation layer and into a second portion of said first opening such that said first portion of said first P tub is in direct mechanical contact with said first source structure within said first opening; and
a second P tub formed within said semiconductor substrate and below said shallow trench isolation layer, wherein said shallow trench isolation layer comprises a second opening, wherein said first drain structure extends from said top surface of said shallow trench isolation layer into a first portion of said second opening, wherein a first portion of said second P tub extends from said bottom surface of said shallow trench isolation layer and into a second portion of said second opening such that said first portion of said second P tub is in direct mechanical contact with said first drain structure within said second opening.
2. The electrical structure of claim 1 , wherein said deep trench, said oxide liner layer, and said first polysilicon fill structure in combination form a first perimeter that circumscribes said first source structure and said first drain structure.
3. The electrical structure of claim 1 , wherein said first gate structure comprises a plurality of gate contacts connected to said first polysilicon fill structure.
4. The electrical structure of claim 1 , wherein said first FET comprises a high voltage FET configured to operate at voltages selected from a range of about 10 volts to about 200 volts.
5. The electrical structure of claim 1 , wherein said first polysilicon fill structure and said oxide liner layer extend through said shallow trench isolation layer and said first P tub into said semiconductor substrate, and wherein said first polysilicon fill structure and said oxide liner layer extend through said shallow trench isolation layer and said second P tub into said semiconductor substrate.
6. The electrical structure of claim 1 , wherein said first gate contact comprises a first silicide contact layer formed over a top surface of said first gate contact.
7. The electrical structure of claim 6 , wherein said first source structure comprises a second silicide contact layer formed over a top surface of said first source structure.
8. The electrical structure of claim 6 , wherein said first drain structure comprises a second silicide contact layer formed over a top surface of said first drain structure.
9. The electrical structure of claim 1 , wherein semiconductor substrate comprises a silicon layer formed over a P substrate.
10. The electrical structure of claim 1 , wherein said first source structure is formed over and not within said semiconductor substrate.
11. The electrical structure of claim 1 , wherein said first drain structure is formed over and not within said semiconductor substrate.
12. The electrical structure of claim 1 , wherein said gate contact is formed over and not within said semiconductor substrate.
13. The electrical structure of claim 1 , wherein said first P tub is in contact with said bottom surface of said shallow trench isolation layer and a first set of vertical surfaces of said shallow trench isolation layer, wherein said bottom surface of said shallow trench isolation layer comprises a horizontal surface, wherein said second P tub is in contact with said bottom surface of said shallow trench isolation layer and a second set of vertical surfaces of said shallow trench isolation layer, and wherein said first set differs from said second set.
14. The electrical structure of claim 1 , wherein said first polysilicon fill structure and said oxide liner layer are formed below and in contact with said bottom surface of said shallow trench isolation layer.