IP Library Granted Patent US 8,969,187
Granted Patent B2
US 8,969,187 · App. 13/859,284 · Granted Mar 3, 2015

Self-aligned contacts

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Quick Facts
Patent No.
US 8,969,187
App. No.
13/859,284
Granted
Mar 3, 2015
Kind
B2
Abstract

A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

Claims (35)

1. A method of forming a gate structure with a self-aligned contact, the method comprising:

encapsulating a location of the gate structure of a channel extending between source and drain regions with lateral spacers and a secondary layer disposed such that an entirety of the secondary layer is between the lateral spacers such that the encapsulated location is defined axially between the lateral spacers and radially between a radially outermost surface of the channel and a radially innermost surface of the secondary layer;

forming silicide in the encapsulated location; and

introducing a conductive material into the encapsulated location through openings formed in the secondary layer.

2. The method according to claim 1 , further comprising forming additional silicide at the source and drain regions.

3. The method according to claim 2 , further comprising decoupling the forming of the silicide in the encapsulated location and the forming of the additional silicide at the source and drain regions from one another.

4. The method according to claim 2 , further comprising depositing an insulator onto the secondary layer and the additional silicide.

5. The method according to claim 4 , further comprising:

opening contact holes at the source and drain regions; and

filling the opened contact holes with contact via material.

6. The method according to claim 1 , further comprising sequentially depositing a sacrificial layer and the secondary layer onto a poly-Si layer at the location of the gate structure, wherein the sacrificial layer comprises germanium.

7. The method according to claim 1 , wherein the secondary layer comprises silicon nitride.

8. The method according to claim 1 , further comprising forming the openings by lithography.

9. The method according to claim 8 , wherein a minimum distance between the openings satisfies an aspect ratio requirement of the silicide forming operation.

10. The method according to claim 1 , wherein the forming of the silicide in the encapsulated location comprises:

depositing silicide forming material by at least one of atomic layer deposition (ALD) and chemical vapor deposition (CVD) in a space formally occupied by a sacrificial layer; and

annealing the silicide forming material to generate the silicide.

11. The method according to claim 10 , wherein the silicide forming material comprises at least one of tungsten (W), platinum (Pt), titanium (Ti), cobalt (Co), nickel (NI) and tantalum (Ta).

12. The method according to claim 10 , further comprising removing excess silicide forming material through the openings.

13. The method according to claim 1 , further comprising:

partially forming the gate structure by forming a high-K gate dielectric layer adjacent to the channel;

forming a conductive layer adjacent the high-K gate dielectric layer; and

providing a poly-Si layer adjacent to the conductive layer.

14. The method according to claim 13 , further comprising defining a space between the poly-Si layer and the secondary layer, wherein the introducing is achieved by at least one of atomic layer deposition (ALD) and chemical vapor deposition (CVD) with respect to the space.

15. A method of forming a gate structure with a self-aligned contact at a predefined location of a channel extending between source and drain regions, the method comprising:

encapsulating the predefined location with lateral spacers and a secondary layer disposed such that an entirety of the secondary layer is between the lateral spacers and such that the encapsulated location is defined axially between the lateral spacers and radially between a radially outermost surface of the channel and a radially innermost surface of the secondary layer with an outer surface of each of the lateral spacers disposed at a corresponding one of the source and drain regions;

forming silicide in the at the encapsulated location; and

introducing a conductive material into the encapsulated location through openings formed in the secondary layer.

16. The method according to claim 15 , further comprising partially forming the gate structure by forming a high-K gate dielectric layer adjacent to the channel, forming a conductive layer adjacent the high-K gate dielectric layer and providing a poly-Si layer adjacent to the conductive layer.

17. The method according to claim 16 , further comprising defining a space between the poly-Si layer and the secondary layer, wherein the introducing comprises at least one of atomic layer deposition (ALD) and chemical vapor deposition (CVD).

18. A method of forming a gate structure with a self-aligned contact at a predefined location of a channel extending between source and drain regions, the method comprising:

encapsulating the predefined location from a section of the source region to a corresponding section of the drain region with lateral spacers and a secondary layer disposed such that an entirety of the secondary layer is between the lateral spacers and such that the encapsulated location is defined axially between the lateral spacers and radially between a radially outermost surface of the channel and a radially innermost surface of the secondary layer;

forming silicide in the encapsulated location; and

introducing a conductive material into the encapsulated location through openings formed in the secondary layer.

19. The method according to claim 18 , further comprising partially forming the gate structure by forming a high-K gate dielectric layer adjacent to the channel, forming a conductive layer adjacent the high-K gate dielectric layer and providing a poly-Si layer adjacent to the conductive layer.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2019
From: GLOBALFOUNDRIES INC.
To: ALSEPHINA INNOVATIONS INC.
Reel/Frame 049612/0211 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2013
From: GUO, DECHAO; HAENSCH, WILFRIED E.A.; HAN, SHU-JEN; LIN, CHUNG-HSUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 031756/0273 →