Layout to minimize FET variation in small dimension photolithography
View Patent ↗A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.
1. A method for improving tracking between FETs (Field Effect Transistor) in an SRAM (Static Random Access Memory) cell on a semiconductor chip produced in a process having a photolithography limitation of 14 nm or smaller minimum feature size requiring a first gate definition mask to define a first set of gates shapes on a gate shape level and a second gate definition mask to define a second set of gate shapes on the gate shape level, the second set of gate shapes interdigitated with the first set of gate shapes on the gate shape level to produce gate shapes on the gate shape level at a minimum pitch supported by the 14 nm photolithography process comprising:
the method comprising:
identifying all FETS in the SRAM cell that require close tracking in FET characteristics; and
laying out the SRAM cell such that all the FETs identified as requiring close tracking are defined by the first gate definition mask on the gate shape level.
2. The method of claim 1 , the SRAM comprising six FETs that must track closely;
the laying out of the circuit comprising defining gates of all six FETs by the first gate definition mask.
3. A method of processing a semiconductor chip comprising a static random access memory (SRAM) further comprising an SRAM cell comprising:
creating a first gate definition mask to define six FET gates on a gate shape level in the SRAM cell;
creating a second gate definition mask to define a seventh FET on the gate shape level;
exposing the semiconductor chip using the first gate definition mask to create the six FET gates in the SRAM cell; and
exposing the semiconductor chip using the second gate definition mask to create the seventh FET;
wherein the processing the semiconductor chip is done by a 14 nm or smaller minimum feature size photolithographic process.