Semiconductor structures and methods of manufacture
View Patent ↗Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.
1. A method, comprising:
forming a metal wiring layer in an organic insulator layer;
forming a protective layer over the organic insulator layer;
forming a via in the organic insulator layer over the metal wiring layer;
depositing a metal layer in the via and on the protective layer; and
patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer,
wherein the metal layer is Al and the patterning is performed using a chlorine based reactive ion etching process;
the metal wiring layer is formed by an electroplating process within a via of an underlying insulator layer;
a layer is formed over the metal wiring layer, and under the organic insulator layer;
the Al layer is formed by a blanket deposition process; and
the forming of the via exposes the metal wiring layer.
2. The method of claim 1 , wherein the organic insulator layer is one of polyimide, BCB (Benzocyclobutene) and PBO (polybenzoxazole).
3. The method of claim 1 , further comprising removing exposed portions of the protective layer after the patterning.
4. The method of claim 3 , wherein the removing of the exposed portions of the protective layer is a fluorine based etching process that minimizes damage to the organic insulator layer.
5. The method of claim 4 , wherein the protective layer is a metal or metal alloy, which has exposed regions which are removed after the patterning of the metal layer.
6. The method of claim 1 , wherein the protective layer is SiO 2 or SiN.
7. A method, comprising:
forming a metal wiring layer in an organic insulator layer;
forming a protective layer over the organic insulator layer;
forming a via in the organic insulator layer over the metal wiring layer;
depositing a metal layer in the via and on the protective layer;
patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer; and
removing exposed portions of the protective layer after the patterning, wherein:
the removing of the exposed portions of the protective layer is a fluorine based etching process that minimizes damage to the organic insulator layer;
the protective layer is a metal or metal alloy, which has exposed regions which are removed after the patterning of the metal layer; and
the metal or metal alloy is one of TaN, TiN and W.
8. The method of claim 7 , wherein the protective layer is formed in the via.