Interconnect structure fabricated without dry plasma etch processing
View Patent ↗An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.
1. A method for fabricating a microelectronic structure comprising:
forming a developable but not imageable bottom anti-reflective coating layer over a substrate that includes a first conductor layer formed within a base dielectric layer;
forming at least one imageable inter-level dielectric layer upon the developable but not imageable anti-reflective coating layer, said at least one imageable inter-level dielectric layer comprising a functionalized polymer having one or more acid-sensitive functional groups; and
imaging and developing the imageable inter-level dielectric layer and developing the developable but not imageable bottom anti-reflective coating layer to form a patterned inter-level dielectric layer formed upon a patterned bottom anti-reflective coating layer that defines an aperture located over the first conductor layer.
2. The method of claim 1 wherein the forming over the substrate uses a dielectric substrate.
3. The method of claim 1 wherein the forming over the substrate uses a semiconductor substrate.
4. The method of claim 1 wherein the aperture comprises a damascene aperture.
5. The method of claim 1 wherein the aperture comprises a dual damascene aperture.
6. The method of claim 1 further comprising forming a second conductor layer within the aperture.
7. The method of claim 1 wherein the developable but not imageable bottom anti-reflective coating layer includes an element selected from the group consisting of C Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La.
8. A method for fabricating a microelectronic structure comprising:
forming a first capping layer self-aligned upon a first conductor layer formed within a base dielectric layer formed over a substrate;
forming a developable but not imageable bottom anti-reflective coating layer over the substrate that includes the first capping layer formed upon the first conductor layer formed within the base dielectric layer;
forming at least one imageable inter-level dielectric layer upon the developable but not imageable bottom anti-reflective coating layer, said at least one imageable inter-level dielectric layer comprising a functionalized polymer having one or more acid-sensitive functional groups; and
imaging and developing the at least one imageable inter-level dielectric layer and developing the developable but not imageable bottom anti-reflective coating layer to form a patterned inter-level dielectric layer formed upon a patterned bottom anti-reflective coating layer that defines an aperture located over the first conductor layer.
9. The method of claim 8 wherein the first conductor layer is formed planarized with respect to the base dielectric layer.
10. The method of claim 8 wherein the first capping layer is formed planarized with respect to the base dielectric layer.
11. The method of claim 8 further comprising forming a second conductor layer into the aperture.
12. The method of claim 8 wherein the developable but not imageable bottom anti-reflective coating layer includes an element selected from the group consisting of C Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La.
13. The method of claim 1 wherein the developable but not imageable bottom anti-reflective coating layer comprises a polymer that includes at least one monomer unit comprising the formula M-R1 wherein M is at least one of C, Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La, and R1 is a chromophore.
14. The method of claim 8 wherein the developable but not imageable bottom anti-reflective coating layer comprises a polymer that includes at least one monomer unit comprising the formula M-R1 wherein M is at least one of C, Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La, and R1 is a chromophore.
15. The method of claim 1 wherein the developable but not imageable bottom anti-reflective coating layer comprises a polymer that includes at least one first monomer unit comprising the formula M-R1 wherein M is at least one of C, Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La, and R1 is a chromophore, and a second monomer unit comprising the formula M′-R2 wherein M′ is at least one of C, Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La and R2 is a cross-linking agent.
16. The method of claim 8 wherein the developable but not imageable bottom anti-reflective coating layer comprises a polymer that includes at least one first monomer unit comprising the formula M-R1 wherein M is at least one of C, Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La, and R1 is a chromophore, and a second monomer unit comprising the formula M′-R2 wherein M′ is at least one of C, Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La and R2 is a cross-linking agent.