Devices and methods of forming finFETs with self aligned fin formation
View Patent ↗Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.
1. A method comprising:
obtaining an intermediate semiconductor device, comprising:
a substrate with at least one shallow trench isolation region;
depositing a hard mask layer over the intermediate semiconductor device;
etching the hard mask layer to form at least one fin hard mask;
depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate;
etching the intermediate semiconductor device to remove a portion of the at least one fin hard mask using the at least one sacrificial gate structure as a mask;
applying a first spacer to the at least one sacrificial gate structure;
forming at least one pFET region in the substrate;
applying a second spacer to the at least one sacrificial gate structure over the first spacer;
forming at least one nFET region in the substrate;
depositing a flowable oxide over the intermediate semiconductor device;
removing the at least one sacrificial gate structure to form at least one opening;
etching over the at least one fin hard mask to form at least one fin in a bottom of the opening; and
removing the at least one fin hard mask.
2. The method of claim 1 , further comprising:
applying a barrier layer to the intermediate semiconductor device over the at least one fin; and
depositing an oxide over the barrier layer.
3. The method of claim 2 , further comprising:
etching the oxide to reveal the at least one fin.
4. The method of claim 3 , further comprising:
etching the barrier layer to form an inner side wall spacer in the at least one opening and to reveal the at least one fin.
5. The method of claim 4 , further comprising:
etching the at least one fin to remove a portion of the at least one fin; and
growing a high mobility channel to replace the removed portion of the at least one fin.
6. The method of claim 4 , further comprising:
depositing a dielectric layer into the at least one opening over the at least one fin; and
depositing a gate material over the dielectric layer.
7. The method of claim 1 , further comprising:
forming at least one fin during a replacement metal gate formation process.