Method for forming semiconductor fuses in a semiconductor device comprising metal gates
View Patent ↗In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment.
1. A method of forming an electronic fuse of a semiconductor device, the method comprising:
forming a layer stack above a first device region and a second device region of said semiconductor device, said layer stack comprising a high-k dielectric material and a semiconductor material;
forming a replacement gate electrode structure above said first device region and a fuse body above said second device region from said layer stack;
increasing an etch resistivity of said semiconductor material selectively in said fuse body; and
performing a wet chemical etch process to remove said semiconductor material selectively in said replacement gate electrode structure, while substantially maintaining said semiconductor material having the increased etch resistivity in said fuse body.
2. The method of claim 1 , wherein increasing an etch resistivity comprises performing an ion implantation process so as to incorporate an electrically inert species into said semiconductor material selectively above said second device region.
3. The method of claim 2 , wherein said electrically inert species comprises xenon.
4. The method of claim 1 , wherein increasing an etch resistivity comprises performing an electron bombardment selectively above said second device region.
5. The method of claim 4 , wherein performing an electron bombardment comprises directing a locally restricted electron beam to said second device region without masking said first device region.
6. The method of claim 1 , further comprising forming a transistor on the basis of said replacement gate electrode structure, forming a dielectric material above said transistor and said fuse body and selectively replacing said semiconductor material after forming said dielectric material.
7. The method of claim 6 , wherein said etch resistivity is increased after forming said dielectric material.
8. The method of claim 7 , further comprising planarizing said dielectric material and exposing said semiconductor material of said replacement gate electrode structure and of said fuse body and wherein said etch resistivity is increased after planarizing said dielectric material.
9. The method of claim 6 , wherein said etch resistivity is increased prior to forming said dielectric material.
10. The method of claim 9 , wherein said etch resistivity is increased prior to forming said replacement gate electrode structure.
11. The method of claim 1 , wherein forming said material layer stack comprises forming a conductive cap layer above said high-k dielectric material.
12. The method of claim 11 , wherein forming said fuse body comprises removing at least said conductive cap layer from above said second device region prior to forming said replacement gate electrode structure and said fuse body.