Electroless fill of trench in semiconductor structure
View Patent ↗A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.
1. A method, comprising:
providing a semiconductor structure comprising a copper-filled trench in a layer of an insulating material, wherein the trench is defined by a bottom and wails, and wherein the copper has one or more undesired voids therein;
removing a portion of the copper from the trench, the portion including the one or more voids and comprising less than all of the copper in the trench; and
electrolessly filling the trench from the bottom upward with additional copper while avoiding copper growth inward from the walls, wherein the electrolessly filling comprises placing the semiconductor structure into an electroless copper solution, and wherein the growing comprises copper from the solution growing on a remaining amount of copper after the removing.
2. The method of claim 1 , wherein the removing comprises performing a chemical etch of the copper in the trench.
3. The method of claim 1 , wherein an amount of copper remaining in the trench after the removing comprises from about 1 nm to about 20 nm.
4. The method of claim 1 , wherein the electrolessly filling comprises placing the semiconductor structure into an electroless copper solution.
5. The method of claim 1 , further comprising planarizing the additional copper after tilling the trench.
6. The method of claim 1 , wherein, the removing comprises leaving a predetermined amount of the copper at the bottom of the trench, and wherein the electrolessly filling comprises growing the additional copper on top of the predetermined amount.
7. The method of claim 1 , wherein the insulating material comprises a silicon oxide-based dielectric.
8. The method of claim 1 , wherein the trench comprises a barrier on the bottom and walls to prevent copper diffusion into the insulating layer.
9. The method of claim 8 , wherein the barrier comprises at least one of tantalum, titanium and tungsten.
10. The method of claim 8 , wherein the trench further comprises a liner on the barrier to promote copper growth.
11. The method of claim 10 , wherein the liner comprises at least one of ruthenium, a ruthenium alloy, cobalt, a cobalt alloy, titanium, a titanium alloy, tungsten, a tungsten alloy, tantalum and a tantalum alloy.
12. A method, comprising:
providing a semiconductor structure comprising a copper-filled trench in a layer of an insulating material, wherein the trench is defined by a bottom and walls, and wherein the copper has one or more undesired voids therein;
removing a portion of the copper from the trench, the portion including the one or more voids and comprising less than all of the copper in the trench; and
electrolessly filling the trench from the bottom upward with additional copper while avoiding copper growth inward from the walls, wherein the electrolessly filling comprises placing the semiconductor structure into an electroless copper solution, and wherein the growing comprises copper from the solution growing on a remaining amount of copper after the removing;
wherein the removing and the electrolessly filling result in a semiconductor structure with a copper-filled trench in the layer of insulating material, the copper having an absence of voids therein.