FinFET fabrication method
View Patent ↗Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.
1. A method of forming a semiconductor structure, comprising:
forming a nitride liner on a semiconductor substrate;
forming a plurality of sacrificial material regions on the nitride liner;
forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions;
removing the plurality of sacrificial material regions;
removing each of the second set of spacers while preserving the first set of spacers; and
forming fins on the semiconductor substrate.
2. The method of claim 1 , wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming a plurality of amorphous silicon regions.
3. The method of claim 1 , wherein forming a first set of spacers and a second set of spacers comprises depositing silicon nitride.
4. The method of claim 1 , wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming a plurality of silicon oxide regions.
5. The method of claim 1 , further comprising:
forming a plurality of shallow trench isolation regions in the semiconductor substrate; and
wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming each sacrificial material region in an off-center alignment with a corresponding shallow trench isolation region.
6. The method of claim 1 , wherein forming a nitride liner comprises forming a nitride liner having a thickness ranging from about 10 nanometers to about 100 nanometers.
7. The method of claim 1 , wherein forming a nitride liner comprises depositing a nitride liner via a chemical vapor deposition process.
8. A method of forming a circuit comprising a plurality of finFET devices, wherein each finFET device comprises a single fin, and wherein each fin of the plurality of finFET devices is formed by:
forming a nitride liner on a semiconductor substrate;
forming a plurality of sacrificial material regions on the nitride liner;
forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions;
removing the plurality of sacrificial material regions;
removing each of the second set of spacers while preserving the first set of spacers, and forming fins on the semiconductor substrate.
9. The method of claim 8 , wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming a plurality of amorphous silicon regions.
10. The method of claim 8 , wherein forming a first set of spacers and a second set of spacers comprises depositing silicon nitride.
11. The method of claim 8 , wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming a plurality of silicon oxide regions.
12. The method of claim 8 , wherein forming a nitride liner comprises forming a silicon nitride liner.
13. The method of claim 8 , further comprising:
forming a plurality of shallow trench isolation regions in the semiconductor substrate; and
wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming each sacrificial material region in an off-center alignment with a corresponding shallow trench isolation region.
14. The method of claim 8 , wherein forming a nitride liner comprises forming a nitride liner having a thickness ranging from about 10 nanometers to about 100 nanometers.
15. The method of claim 8 , wherein forming a nitride liner comprises depositing a nitride liner via a chemical vapor deposition process.
16. A method of forming a semiconductor structure, comprising:
forming a nitride liner on a semiconductor substrate;
forming a plurality of sacrificial material regions on the nitride liner;
wherein a pitch between adjacent sacrificial material regions ranges from about 50 nanometers to about 90 nanometers;
forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions;
removing the plurality of sacrificial material regions;
removing each of the second set of spacers while preserving the first set of spacers; and
forming fins on the semiconductor substrate.
17. The method of claim 16 , wherein forming a plurality of sacrificial material regions comprises forming sacrificial material regions having a width ranging from about 15 nanometers to about 30 nanometers.
18. The method of claim 16 , wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming a plurality of amorphous silicon regions.
19. The method of claim 16 , wherein forming a nitride liner comprises forming a silicon nitride liner.
20. The method of claim 16 , further comprising:
forming a plurality of shallow trench isolation regions in the semiconductor substrate; and
wherein forming a plurality of sacrificial material regions on the nitride liner comprises forming each sacrificial material region in an off-center alignment with a corresponding shallow trench isolation region.