Semiconductor device having a grain orientation layer
View Patent ↗A manufacturing process of a semiconductor device includes generating a less random grain orientation distribution in metal features of a semiconductor device by employing a grain orientation layer. The less random grain orientation, e.g., a grain orientation distribution which has a higher percentage of grains that have a predetermined grain orientation, may lead to improved reliability of the metal features. The grain orientation layer may be deposited on the metal features wherein the desired grain structure of the metal features may be obtained by a subsequent annealing process, during which the metal feature is in contact with the grain orientation layer.
1. A method, comprising:
providing a substrate having a metallization layer with at least one metal feature, wherein said substrate comprises a dielectric material layer having a recess and providing a substrate having a metallization layer comprises depositing a metal feature material in said recess by overfilling said recess with said metal feature material, thereby depositing metal feature material above a surface of said dielectric material and planarizing said substrate after depositing said metal feature material, thereby removing metal feature material extending above said surface of said dielectric material;
forming a grain orientation layer above said metal feature and in direct contact with said metal feature after planarizing said substrate, wherein said grain orientation layer comprises a material different than said metal feature;
annealing said metal feature after forming said grain orientation layer to thereby increase a percentage of grains in said metal feature which have said predetermined grain orientation, wherein, during said annealing, said grain orientation layer energetically favors a predetermined grain orientation of grains in said metal feature compared to other grain orientations of grains in said metal feature; and
selectively removing said grain orientation layer after said annealing of said metal feature, wherein grain orientation layer material of said grain orientation layer diffused into said metal feature is completely removed during the removing of said grain orientation layer.
2. The method of claim 1 , wherein said metal feature comprises copper.
3. The method of claim 1 , wherein said grain orientation layer is a metal layer.
4. The method of claim 1 , wherein said grain orientation layer is a dielectric layer.
5. The method of claim 1 , further comprising forming a capping layer over said metal feature after removing said grain orientation layer.
6. The method of claim 1 , wherein the grain orientation layer is deposited by employing deposition parameters such that said grain orientation layer has a predominant grain orientation.
7. The method of claim 1 , wherein, during said annealing, the grain orientation layer has an elastic modulus which is higher than an elastic modulus of said metal feature.
8. The method of claim 1 , wherein, during said annealing, a hardness of said grain orientation layer is greater than a hardness of said metal feature.
9. The method of claim 1 , wherein said at least one metal feature comprises a metal line.
10. The method of claim 1 , wherein said at least one metal feature comprises a via plug for electrically connecting metal features of two different levels.