Embedded on-chip security
View Patent ↗Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.
1. A semiconductor device, comprising:
a dielectric layer disposed on a substrate; and
a randomly patterned interconnect structure for implementing a physical unclonable function (PUF), the randomly patterned interconnect structure being disposed in the dielectric layer, and the randomly patterned interconnect structure comprising:
an array of conductive elements organized in a uniform grid pattern,
wherein each of the conductive elements have a first rectangular shape in a top view, the first rectangular shape defined by a long side aligned longitudinally with a first direction and a short side aligned longitudinally with a second direction perpendicular to the first direction, and
wherein the short side is only in direct physical contact with the dielectric layer,
an array of connection regions randomly located, respectively, in the uniform grid pattern between first pairs of adjacent ones of the conductive elements,
wherein each of the connection regions have a second rectangular shape in the to view, the second rectangular shape defined by a first side and a second side,
wherein the first side is only in direct physical contact with the long side of a respective one of the first pairs of the adjacent ones of the conductive elements,
wherein each of the connection regions electrically connects, along the second direction, the respective one of the first pairs of the adjacent ones of the conductive elements, and
wherein the second side is aligned longitudinally with the second direction and only in direct physical contact with the dielectric layer, and
an array of insulation regions randomly located, respectively, in the uniform grid pattern and between second pairs of the adjacent ones of the conductive elements,
wherein each of the insulation regions comprise a respective portion of the dielectric layer and insulate a respective one of the second pairs of the adjacent ones of the conductive elements.
2. The semiconductor device of claim 1 , wherein the array of conductive elements comprises an array of metal wire segments.
3. The semiconductor device of claim 1 , wherein the substrate comprises silicon, silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide, an alloy of silicon and germanium, or indium phosphide.
4. The semiconductor device of claim 1 , wherein the dielectric layer comprises Fluorosilicate glass (FSG), carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, spin-on organic polymeric dielectrics, or spin-on silicone based polymeric dielectric.
5. The semiconductor device of claim 1 , wherein the electrically conductive portions of the randomly patterned interconnect structure comprise copper or aluminum.