Angle ion implant to re-shape sidewall image transfer patterns

1. A method for fabrication of features for an integrated circuit, comprising:

patterning a first structure on a surface of a semiconductor device;

forming spacers about a periphery of the first structure;

applying an angled ion implantation to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions;

selectively removing the unprotected portions and the first structure with respect to the protected portions; and

patterning a layer below the protected portions of the spacer to form integrated circuit features.

2. The method as recited in claim 1 , wherein patterning a layer below the protected portions of the spacers to form integrated circuit features includes forming fins in the layer below the protected portions of the spacer.

3. The method as recited in claim 2 , wherein the semiconductor device includes a silicon-on-insulator structure and the step of forming fins includes forming fins in a silicon on oxide layer below the protected portions of the spacer.

4. The method as recited in claim 2 , wherein forming fins includes forming fins in an oxide mask and a silicon on oxide layer below the protected portions of the spacer such that upon removal of the spacers the mask oxide includes material unattacked by prior processing.

5. The method as recited in claim 1 , wherein the applying an angled ion implantation include selecting an angle of attack and direction of ion implantation to modify a shape of exposed spacers.

6. The method as recited in claim 1 , wherein the first structure includes a mandrel patterned using a lithographic method such that a width of the mandrel includes a minimum feature size achievable by the lithographic method.

7. The method as recited in claim 6 , wherein the spacer includes a width of less than the minimum feature size.

8. A method for fabrication of features for an integrated circuit, comprising:

patterning one or more mandrel structures on a surface of a semiconductor device;

forming sidewall spacers about a periphery of the one or more mandrel structures;

applying an angled ion implantation to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions;

selectively removing the unprotected portions and the one or more mandrel structures with respect to the protected portions;

opening a mask layer disposed below the protected portions of the spacer by etching to expose a layer beneath the mask layer;

removing remaining portions of the spacer;

forming fins in the layer beneath the mask layer by employing remaining portions of the mask layer as a mask; and

forming integrated circuit features using the fins.

9. The method as recited in claim 8 , wherein the semiconductor device includes a silicon on insulator structure and the step of forming fins includes forming fins in a silicon on oxide layer.

10. The method as recited in claim 8 , wherein upon removing remaining portions of the spacer, the mask layer includes material unattacked by prior processing.

11. The method as recited in claim 8 , wherein the applying an angled ion implantation includes selecting an angle of attack and direction of ion implantation to modify a shape of exposed spacers.

12. The method as recited in claim 8 , wherein the one or more mandrel structures are patterned using a lithographic method such that a width of a mandrel includes a minimum feature size achievable by the lithographic method.

13. The method as recited in claim 12 , wherein the spacer includes a width of less than the minimum feature size.

14. A method for fabrication of features on an integrated circuit, comprising:

patterning one or more polysilicon mandrel structures on a surface of a silicon-on-insulator substrate having and mask oxide layer formed thereon;

forming nitride sidewall spacers about a periphery of the one or more mandrel structures;

applying an angled ion implantation to the spacers, which have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions;

selectively removing the unprotected portions and the one or more mandrels with respect to the protected portions;

opening the mask oxide layer between the protected portions of the spacer by etching;

removing remaining portions of the spacer;

forming fins in a silicon layer below the mask oxide layer by employing remaining portions of the mask oxide layer as a mask; and

forming field effect transistors using the fins.

15. The method as recited in claim 14 , wherein upon removing remaining portions of the spacer, the mask layer includes material unattacked by prior processing.

16. The method as recited in claim 14 , wherein the applying an angled ion implantation includes selecting an angle of attack and direction of ion implantation to modify a shape of exposed spacers.

17. The method as recited in claim 14 , wherein the one or more mandrel structures are patterned using a lithographic method such that a width of a mandrel includes a minimum feature size achievable by the lithographic method.

18. The method as recited in claim 17 , wherein the spacer includes a width of less than the minimum feature size.