eFUSE enablement with thin polysilicon or amorphous-silicon gate-stack for HKMG CMOS
View Patent ↗An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting.
1. A method of fabricating a semiconductor, the method comprising:
forming a shallow trench isolation (STI) region in a substrate;
forming a first gate stack on the substrate by:
forming a metal electrode,
forming a polysilicon layer on the metal electrode, and
forming a nitride cap on the polysilicon layer;
forming a second gate stack on an STI region by:
forming a metal electrode,
forming a polysilicon layer on the metal electrode, and
forming a nitride cap on the polysilicon layer;
forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack; and
forming second eSiGe on the second gate stack.
2. The method according to claim 1 , comprising:
forming the first and second eSiGe simultaneously.
3. The method according to claim 1 , further comprising removing the nitride cap from the second gate stack prior to forming the second eSiGe.
4. The method according to claim 3 , comprising forming the second eSiGe and the polysilicon layer of the second gate stack to a total thickness of about 100 nm to about 140 nm.
5. The method according to claim 4 , comprising forming the polysilicon layer of the second gate stack to a thickness of about 60 nm to about 80 nm.
6. The method according to claim 4 , further comprising forming a silicide on the first and second eSiGe.
7. The method according to claim 6 , comprising forming the silicide on the second eSiGe to a thickness of about 20 nm to about 30 nm.
8. A semiconductor device comprising:
a substrate;
a first gate stack on the substrate, the first gate stack comprising:
a metal electrode, and
a polysilicon layer on the metal electrode;
a shallow trench isolation region on the substrate, separate from the first gate stack; and
an eFUSE on the shallow trench isolation region, the eFUSE comprising:
a metal electrode;
a polysilicon layer on the metal electrode; and
an embedded silicon germanium (eSiGe) on the polysilicon layer.
9. The semiconductor device according to claim 8 , further comprising an eSiGe on the substrate on first and second sides of the first gate stack.
10. The semiconductor device according to claim 9 , wherein the eSiGe and polysilicon layer of the eFUSE have a total thickness of about 100 nm to about 140 nm.
11. The semiconductor device according to claim 10 , wherein the polysilicon layer of the eFUSE has a thickness of about 60 nm to about 80 nm.
12. The semiconductor device according to claim 10 , further comprising a silicide on the eSiGe of the eFUSE and on the eSiGe on the substrate.
13. The semiconductor device according to claim 12 , wherein the silicide of the eFUSE has a thickness of about 20 nm to about 30 nm.
14. A method of fabricating a semiconductor device comprising:
forming an NMOS gate stack and a PMOS gate stack on a substrate;
forming a shallow trench isolation (STI) region in the substrate;
forming an eFUSE gate stack on the STI region, each of the NMOS, PMOS, and eFUSE gate stacks comprising a metal electrode and a polysilicon layer on the metal electrode;
forming embedded silicon germanium (eSiGe) source/drain regions on first and second sides of the PMOS gate stack;
forming eSiGe on the eFUSE gate stack; and
forming a silicide on the eSiGe source/drain regions and on the eSiGe on the eFUSE gate stack.
15. The method according to claim 14 , comprising forming the eSiGe and polysilicon layer of the eFUSE gate stack to a total thickness of about 100 nm to about 140 nm.
16. The method according to claim 15 , comprising forming the polysilicon layer of the eFUSE gate stack to a thickness of about 60 nm to about 80 nm.
17. The method according to claim 16 , comprising forming the silicide on the eFUSE eSiGe to a thickness of about 20 nm to about 30 nm.
18. The method according to claim 14 , comprising forming the eSiGe source drain regions and the eSiGe on the eFUSE gate stack simultaneously.