PFET with tailored dielectric and related methods and integrated circuit

1. A method comprising:

providing an implanted substrate including an n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region;

forming a mask over the NMOS region;

epitaxially growing a layer including silicon and doping or implanting the layer including silicon to form a doped band engineered p-type field effect transistor (PFET) threshold voltage (Vt) work function tuning layer over the PMOS region only;

removing the mask to expose the NMOS region of the implanted substrate;

forming a high dielectric constant layer over the NMOS region of the implanted substrate and the PFET Vt work function tuning layer;

forming an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer;

forming a metal layer over the NFET Vt work function tuning layer; and

patterning a first gate over the NMOS region and a second gate over the PMOS region, the second gate including the doped band engineered PFET Vt work function tuning layer directly over the PMOS region, the high dielectric constant layer directly over the doped band engineered PFET Vt work function tuning layer, and the NFET Vt work function tuning layer directly over the high dielectric constant layer.

2. The method of claim 1 , further comprising annealing, causing the NFET Vt work function tuning layer to blend with the high dielectric constant layer to form a single layer.

3. The method of claim 1 , wherein the doped band engineered PFET Vt work function tuning layer includes boron doped silicon germanium in the case that the layer including silicon is doped.

4. The method of claim 1 , wherein the NFET Vt work function tuning layer is selected from the group consisting of: lanthanum oxide, barium oxide, magnesium oxide and strontium oxide.

5. The method of claim 1 , wherein the high dielectric constant layer is selected from the group consisting of: hafnium dioxide, hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4) and silicon oxynitride (SiON).

6. The method of claim 1 , wherein the metal layer is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN) and tantalum silicon nitride (TaSiN).

7. A p-type field effect transistor (PFET) comprising:

an n-type doped silicon well (N-well); and

a gate stack including:

a doped band engineered PFET threshold voltage (Vt) work function tuning layer directly over the N-well;

a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer including a high dielectric constant layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer directly over and having been annealed with the high dielectric constant layer; and

a metal over the NFET Vt work function tuning layer.

8. The PFET of claim 7 , wherein the doped band engineered PFET Vt work function tuning layer includes boron or fluorine doped silicon germanium.

9. The PFET of claim 7 , wherein the NFET Vt work function tuning layer is selected from the group consisting of: lanthanum oxide, barium oxide, magnesium oxide and strontium oxide.

10. The PFET of claim 7 , wherein the high dielectric constant layer is selected from the group consisting of: hafnium dioxide, hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4) and silicon oxynitride (SiON).

11. The PFET of claim 7 , wherein the metal layer is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN) and tantalum silicon nitride (TaSiN).

12. An integrated circuit (IC) comprising:

a p-type field effect transistor (PFET) including:

an n-type doped silicon well (N-well); and

a gate stack including:

a doped band engineered PFET threshold voltage (Vt) work function tuning layer directly over the N-well;

a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer including a high dielectric constant layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer directly over and having been annealed with the high dielectric constant layer; and

a metal over the tailored dielectric layer.

13. The IC of claim 12 , further comprising an n-type field effect transistor (NFET) adjacent to the PFET, the NFET including:

an p-type doped silicon well (P-well);

a gate stack including the high dielectric constant layer over the p-well and the metal over the tailored dielectric layer.

14. The IC of claim 13 , further comprising an isolation region between the PFET and the NFET.

15. The IC of claim 12 , wherein the doped band engineered PFET Vt work function tuning layer includes boron or fluorine doped silicon germanium.

16. The IC of claim 12 , wherein the NFET Vt work function tuning layer is selected from the group consisting of: lanthanum oxide, barium oxide, magnesium oxide and strontium oxide.

17. The IC of claim 12 , wherein the high dielectric constant layer is selected from the group consisting of: hafnium dioxide, hafnium silicate (HfSiOx), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4) and silicon oxynitride (SiON).

18. The IC of claim 12 , wherein the metal layer is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN) and tantalum silicon nitride (TaSiN).