Structure and method to minimize regrowth and work function shift in high-k gate stacks
View Patent ↗The present invention provides a semiconductor structure comprising high-k material portions that are self-aligned with respect to the active areas in the semiconductor substrate and a method of fabricating the same. The high-k material is protected from oxidation during the fabrication of the semiconductor structure and regrowth of the high-k material and shifting of the high-k material work function is prevented.
1. A method of forming a semiconductor structure comprising: forming an interface layer on a semiconductor substrate; forming a high-k material layer on the interface layer; forming a silicon nitride layer on the high-k material layer; developing a shallow trench in the semiconductor structure by photolithography and etching or pattern transfer; forming a trench liner on the semiconductor structure; depositing a shallow trench isolation; removing the silicon nitride layer; and further comprising forming a metallic layer on the high-k material layer and forming the silicon nitride layer on the metallic layer instead of the high-k material layer,
wherein the metallic layer is removed concurrently with, or subsequent to, the removing of the silicon nitride layer.
2. The method of claim 1 , further comprising converting the interface layer into a nitride containing layer.
3. The method of claim 1 , further comprising forming a silicon layer on the metallic layer and forming the silicon nitride layer on the silicon layer instead of the metallic layer,
wherein the silicon layer is one of an amorphous silicon layer and a polycrystalline silicon layer, and
wherein the silicon layer is removed concurrently with, or subsequent to, the removing of the silicon nitride layer.
4. The method of claim 1 , wherein the semiconductor substrate is a doped semiconductor material.
5. The method of claim 1 , wherein the trench liner is oxygen-impermeable.
6. The method of claim 1 , wherein the trench liner is U-shaped.
7. The method of claim 1 , wherein the silicon nitride layer is removed by treatment with hot phosphoric acid.
8. The method of claim 1 , wherein the shallow trench recess is developed by dry etching.
9. The method of claim 1 , wherein the semiconductor structure is planarized by a chemical mechanical polishing prior to the developing of the trench isolation recess.
10. The method of claim 1 , wherein the trench liner is deposited by atomic layer deposition (ALD).