IP Library Granted Patent US 9,087,772
Granted Patent B2
US 9,087,772 · App. 13/611,387 · Granted Jul 21, 2015

Device and method for forming sharp extension region with controllable junction depth and lateral overlap

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Quick Facts
Patent No.
US 9,087,772
App. No.
13/611,387
Granted
Jul 21, 2015
Kind
B2
Abstract

A method for forming a semiconductor device includes forming a gate stack on a monocrystalline substrate. A surface of the substrate adjacent to the gate stack and below a portion of the gate stack is amorphorized. The surface is etched to selectively remove a thickness of amorphorized portions to form undercuts below the gate stack. A layer is epitaxially grown in the thickness and the undercuts to form an extension region for the semiconductor device. Devices are also provided.

Claims (9)

1. A semiconductor device, comprising:

a gate electrode formed on a monocrystalline substrate over a channel region;

extension diffusion layers formed by crystal growth on top of a surface of the monocrystalline substrate on opposing sides of the channel region, each extension diffusion layer having a portion extending into an undercut formed in an implantation region underneath the gate electrode, wherein the undercut is angled such that a bottom surface of bottom portions of each extension diffusion layer extends horizontally farther underneath the gate electrode than top portions of the extension diffusion layer; and

source and drain diffusion regions formed in contact with the extension diffusion layers.

2. The semiconductor device as recited in claim 1 , wherein the extension diffusion layers includes a crystal structure formed on top of the surface of the monocrystalline substrate by epitaxial growth.

3. The semiconductor device as recited in claim 1 , wherein source and drain diffusion regions are formed below the extension diffusion layers in the monocrystalline substrate.

4. The semiconductor device as recited in claim 1 , wherein source and drain diffusion regions include raised regions formed on the extension diffusion layers.

5. The semiconductor device as recited in claim 1 , wherein the extension diffusion layers include a thickness of about 10 nm.

6. The semiconductor device as recited in claim 1 , wherein the undercut is angled between about 5 and about 20 degrees with respect to the vertical direction of the gate electrode.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2019
From: GLOBALFOUNDRIES INC.
To: ALSEPHINA INNOVATIONS INC.
Reel/Frame 049612/0211 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →