Methods of forming a PMOS device with in situ doped epitaxial source/drain regions
View Patent ↗Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process.
1. A method of forming a PMOS device and an NMOS device in and above a PMOS region and an NMOS region, respectively, of a semiconducting substrate, the method comprising:
forming extension implant regions in said PMOS region and said NMOS region of said semiconducting substrate for said PMOS device and said NMOS device, respectively;
after forming said extension implant regions, performing a first heating process;
forming a plurality of cavities in said PMOS region of said substrate;
performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities;
forming a masking layer that exposes said NMOS region and covers said PMOS region;
after forming said plurality of said in-situ doped semiconductor layers, forming source/drain implant regions in said NMOS region of said substrate for said NMOS device; and
after forming said source/drain implant regions in said NMOS region, performing a second heating process.
2. The method of claim 1 , wherein performing said at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers comprises:
forming a first semiconductor layer on at least a bottom surface of each of said cavities, said first semiconductor layer having a first dopant concentration of a P-type dopant material; and
forming a second semiconductor layer on said first semiconductor layer, said second semiconductor layer having a second dopant concentration of a P-type dopant material that is greater than said first dopant concentration of P-type dopant.
3. The method of claim 2 , wherein said first layer of semiconductor material is a layer of silicon germanium with a first concentration of germanium, and said second layer of semiconductor material is a layer of silicon germanium having a second concentration of germanium that is greater than said first concentration of germanium.
4. The method of claim 3 , wherein said first concentration of germanium is 25% or less and said second concentration of germanium that is 30% or greater.
5. The method of claim 4 , wherein each of said plurality of in-situ doped semiconductor layers is doped with a P-type dopant material.
6. The method of claim 2 , wherein said first dopant concentration of P-type dopant material ranges from 1e 19 -5e 19 ions/cm 3 , and said second dopant concentration of P-type dopant material ranges from 2e 20 -5e 20 ions/cm 3 .
7. The method of claim 2 , wherein performing said at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers further comprises forming a third layer of semiconductor material on at least said second layer of semiconductor material, said third layer of semiconductor material having a third dopant concentration of a P-type dopant material that is greater than said first dopant concentration of P-type dopant.
8. The method of claim 7 , wherein said second and third dopant concentrations of a P-type dopant material are approximately the same.
9. The method of claim 1 , where each of said plurality of in-situ doped semiconductor layers are doped with the same P-type dopant material.
10. The method of claim 9 wherein said dopant material is boron.
11. The method of claim 1 , wherein said first heating process is one of a rapid thermal anneal process or an ultra-fast anneal process.
12. The method of claim 1 , wherein said second heating process is an ultra-fast anneal process performed at a temperature of at least approximately 1200-1300 C for a duration of at least one millisecond.
13. A method of forming a PMOS device and an NMOS device in and above a PMOS region and an NMOS region, respectively, of a semiconducting substrate, the method comprising:
forming extension implant regions in said PMOS region and said NMOS region of said semiconducting substrate for said PMOS device and said NMOS device, respectively;
after forming said extension implant regions, performing a first heating process;
forming a plurality of cavities in said PMOS region of said substrate;
performing a first epitaxial deposition process to form a first in-situ doped layer of silicon germanium on at least a bottom surface of each of said cavities, said first layer of silicon germanium having a first dopant concentration of a P-type dopant material;
performing a second epitaxial deposition process to form a second in-situ doped layer of silicon germanium on said first layer of silicon germanium, said second layer of silicon germanium having a second dopant concentration of a P-type dopant material that is greater than said first dopant concentration of a P-type dopant material;
performing a third epitaxial deposition process to form an in-situ doped layer of silicon on at least said second layer of silicon germanium wherein said layer of silicon has a third dopant concentration of a P-type dopant material that is greater than said first dopant concentration of P-type dopant;
forming a masking layer that exposes said NMOS region and covers said PMOS region;
after performing said third epitaxial deposition process, forming source/drain implant regions in said NMOS region of said substrate for said NMOS device; and
after forming said source/drain implant regions in said NMOS region, performing a second heating process.
14. The method of claim 13 , wherein said first layer of silicon germanium has a first concentration of germanium, and said second layer of silicon germanium having a second concentration of germanium that is greater than said first concentration of germanium.
15. The method of claim 14 , wherein said first concentration of germanium is 25% or less and said second concentration of germanium that is 30% or greater.
16. The method of claim 13 , wherein said first dopant concentration of P-type dopant material ranges from 1e 19 -5e 19 ions/cm 3 , and said second dopant concentration of P-type dopant material ranges from 2e 20 -5e 20 ions/cm 3 .
17. The method of claim 13 , wherein said second and third dopant concentrations of a P-type dopant material are approximately the same.
18. The method of claim 16 , where each of said first layer of silicon germanium, said second layer of silicon germanium and said layer of silicon are doped with the same P-type dopant material.
19. The method of claim 18 wherein said dopant material is boron.
20. The method of claim 13 , wherein said first heating process is one of a rapid thermal anneal process or an ultra-fast anneal process.
21. The method of claim 13 , wherein said second heating process is an ultra-fast anneal process performed at a temperature of at least approximately 1200-1300 C for a duration of at least one millisecond.