Method for growing strain-inducing materials in CMOS circuits in a gate first flow
View Patent ↗A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.
1. A circuit structure comprising:
a substrate comprising a first region and a second region;
an isolation region in said substrate positioned laterally between said first region and said second region;
a gate conductor traversing said first region, said isolation region and said second region, said gate conductor comprising a first portion for a first transistor on said first region, a second portion for a second transistor on said second region, and an additional portion on said isolation region and extending laterally between said first portion and said second portion;
a first conformal insulator layer immediately adjacent to said first portion, said additional portion and said second portion of said gate conductor; and
a second conformal insulator layer on said first conformal insulator layer positioned over said second portion and extending laterally over said additional portion of said gate conductor such that said second conformal insulator layer has an end above said additional portion of said gate conductor.
2. The circuit structure according to claim 1 , said second conformal insulator layer being thinner than said first conformal insulator layer.
3. The circuit structure according to claim 1 , said second conformal insulator layer comprising a molecular layer.
4. The circuit structure according to claim 1 , said second conformal insulator layer having a thickness from about 3 nm to about 9 nm.
5. The circuit structure according to claim 1 , said the first transistor comprising a P-type transistor and said second transistor comprising an N-type transistor.
6. The structure according to claim 1 , said second conformal insulator layer comprising a same insulator material as said first conformal insulator layer such that a first thickness of said insulator material on said additional portion of said gate conductor adjacent to said first transistor is less than a second thickness of said insulator material on said additional portion of said gate conductor adjacent to said second transistor.
7. The circuit structure according to claim 1 , said second conformal insulator layer comprising a different insulator material than said first conformal insulator layer.
8. The circuit structure according to claim 1 ,
said first region comprising: first source/drain regions and a first channel region positioned laterally between said first source/drain regions and aligned below said first portion of said gate conductor, said first source/drain regions comprising first trenches filled with a first epitaxial semiconductor layer that causes a first type of strain in said first channel region, and
said second region comprising: second source/drain regions and a second channel region positioned laterally between said second source/drain regions and aligned below said second portion of said gate conductor, said second source/drain regions comprising second trenches filled with a second epitaxial semiconductor layer different from said first epitaxial semiconductor layer, said second epitaxial semiconductor layer causing a second type of strain different from said first type of strain in said second channel region.
9. A circuit structure comprising:
a substrate comprising a first region and a second region,
said first region comprising: for a first transistor, first source/drain regions and a first channel region positioned laterally between said first source/drain regions, said first source/drain regions comprising first trenches filled with a first epitaxial semiconductor layer that causes a first type of strain in said first channel region, and
said second region comprising: for a second transistor, second source/drain regions and a second channel region positioned laterally between said second source/drain regions, said second source/drain regions comprising second trenches filled with a second epitaxial semiconductor layer different from said first epitaxial semiconductor layer such that said second epitaxial semiconductor layer causes a second type of strain different from said first type of strain in said second channel region;
an isolation region in said substrate positioned laterally between said first region and said second region;
a gate conductor traversing said first region, said isolation region and said second region, said gate conductor comprising a first portion on said first channel region, a second portion on said second channel region, and an additional portion on said isolation region and extending laterally between said first portion and said second portion;
a first conformal insulator layer immediately adjacent to said first portion, said additional portion, and said second portion of said gate conductor; and
a second conformal insulator layer on said first conformal insulator layer positioned over said second portion and extending laterally over said additional portion of said gate conductor such that said second conformal insulator layer has an end above said additional portion of said gate conductor.
10. The circuit structure according to claim 9 , said second conformal insulator layer being thinner than said first conformal insulator layer.
11. The circuit structure according to claim 9 , said second conformal insulator layer comprising a molecular layer.
12. The circuit structure according to claim 9 , said second conformal insulator layer having a thickness from about 3 nm to about 9 nm.
13. The circuit structure according to claim 9 , said the first transistor comprising a p-type transistor and said second transistor comprising an n-type transistor.
14. A circuit structure comprising:
a substrate comprising a first region and a second region;
an isolation region in said substrate positioned laterally between said first region and said second region;
a gate conductor traversing said first region, said isolation region and said second region, said gate conductor comprising a first portion for a first transistor on said first region, a second portion for a second transistor on said second portion, and an additional portion on said isolation region and extending laterally between said first portion and said second portion;
a first conformal insulator layer immediately adjacent to said first portion, said second portion and said additional portion of said gate conductor; and,
a second conformal insulator layer on said first conformal insulator layer positioned over said second portion and extending laterally over said additional portion of said gate conductor such that said second conformal insulator has an end above said additional portion of said gate conductor,
said second conformal insulator layer comprising a same insulator material as said first conformal insulator layer such that a first thickness of said insulator material on said additional portion of said gate conductor adjacent to said first transistor is less than a second thickness of said insulator material on said additional portion of said gate conductor adjacent to said second transistor.
15. The circuit structure according to claim 14 , said second conformal insulator layer being thinner than said first conformal insulator layer.
16. The circuit structure according to claim 14 , said second conformal insulator layer comprising a molecular layer.
17. The circuit structure according to claim 14 , said second conformal insulator layer having a thickness from about 3 nm to about 9 nm.
18. The circuit structure according to claim 14 , said the first transistor comprising a p-type transistor and said second transistor comprising an n-type transistor.
19. The circuit structure according to claim 14 ,
said first region comprising: first source/drain regions and a first channel region positioned laterally between said first source/drain regions and aligned below said first portion of said gate conductor, said first source/drain regions comprising first trenches filled with a first epitaxial semiconductor layer that causes a first type of strain in said first channel region, and
said second region comprising: second source/drain regions and a second channel region positioned laterally between said second source/drain regions and aligned below said second portion of said gate conductor, said second source/drain regions comprising second trenches filled with a second epitaxial semiconductor layer different from said first epitaxial semiconductor layer, said second epitaxial semiconductor layer causing a second type of strain different from said first type of strain in said second channel region.