Asymmetric FinFET devices
View Patent ↗Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.
1. Field Effect Transistor (FET) devices, comprising:
a fin of a semiconductor material, wherein said fin has a first side surface opposite a second side surface;
a first FET device hosted on said first side surface and a second FET device hosted on said second side surface, wherein said first FET device and said second FET device comprise gate insulators and gates, wherein said gate insulators comprise a same high-k dielectric, and said gates comprise a same gate conductor;
a threshold-modifying layer over said high-k dielectric of said second FET device; and
wherein said first and said second FET device are FinFET devices having an asymmetry due to said threshold-modifying layer being absent in said first FET device.
2. Field Effect Transistor (FET) devices, comprising:
a fin of a semiconductor material, wherein said fin has a first side surface opposite a second side surface;
a first FET device hosted on said first side surface and a second FET device hosted on said second side surface, wherein said first FET device and said second FET device comprise gate insulators and gates, wherein said gate insulators comprise a same high-k dielectric, and said gates comprise differing gate conductors; and
wherein said first and said second FET device are FinFET devices manifesting an asymmetry due to said gates comprising said differing gate conductors.
3. The FET devices of claim 2 , further comprising a first threshold-modifying layer over said high-k dielectric of said second FET device, wherein said first and said second FET device further manifesting said asymmetry due to said first threshold-modifying layer being absent in said first FET device.
4. The FET devices of claim 2 , further comprising a second threshold-modifying layer over said high-k dielectric of said first FET device, wherein said first and said second FET device further manifesting said asymmetry due to said second threshold-modifying layer being in differing locations in said first and said second FET device.