Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures
View Patent ↗The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).
1. A semiconductor chip including a semiconductor substrate, the semiconductor substrate comprising:
a first major surface in which a semiconductor device has been formed,
a second major surface opposite to said first major surface, said second major surface created by thinning said semiconductor substrate,
a through-silicon-via (TSV) extending between the first and the second major surface, and
bulk micro defects (BMD) having an average size less than 55 nm (nanometers) within a first region of said semiconductor substrate, said first region being within ten microns of said second major surface, said BMD having a density greater than 1e4/cc (particles per cubic centimeter) and less than 1e7/cc throughout a second region traversed by the TSV, said second region extending between the first and the second major surface.
2. The semiconductor chip of claim 1 further comprising:
crystal originated defects in said region.
3. The semiconductor chip of claim 1 wherein:
all of said BMD have an equivalent diameter less than or equal to 55 nm.
4. The semiconductor chip of claim 1 wherein:
Said BMD have an average equivalent diameter in the range of 20 nm to 35 nm.
5. The semiconductor chip of claim 4 wherein
said conductive path connects to a semiconductor device formed on a second chip, and
said second chip is bonded to said semiconductor chip to form a 3D IC.
6. The semiconductor chip of claim 1 wherein at least one passive semiconductor device is formed in said first major surface.
7. An integrated circuit structure comprising,
a first chip bonded to a second chip wherein
said first chip includes a plurality of semiconductor devices,
said second chip includes a front surface in which at least one semiconductor device is formed, a back surface opposite to said front surface, and a through substrate via (TSV) that extends at least from said front surface to said back surface, and
said second chip includes BMD at a density between 1e4/cc and 1e7/cc in a region bounded by said back surface, the region traversed by the TSV and extending between said front surface and said back surface.
8. The integrated circuit structure of claim 7 wherein said region includes all of said second chip except a denuded zone.
9. The integrated circuit structure of claim 7 wherein said region includes the entirety of said second chip between said front surface and said back surface.
10. The integrated circuit structure of claim 7 wherein
said first substrate includes a region in which BMD density is greater than 1e9/cc.
11. A 3D integrated circuit comprising:
a first chip bonded to a second chip wherein
said first chip includes first BMD in an interior region, such first BMD having an
average equivalent diameter greater than 70 nm, and
said second chip includes second BMD having average equivalent diameter smaller than 50 nm, a through-silicon-via (TSV) extending throughout the second chip, said second BMD having a density greater than 1e4/cc (particles per cubic centimeter) and less than 1e7/cc throughout a region traversed by the TSV, said region extending between a front side and a back side of the second chip.
12. The 3D integrated circuit of claim 11 further comprising
a third chip, wherein said third chip has an average BMD size in the range of 20 nm to 50 nm.
13. The 3D integrated circuit of claim 11 wherein said second chip includes a second chip substrate which second chip substrate has a thickness between 20 and 100 um (microns).
14. The 3D integrated circuit of claim 11 wherein said first chip includes a plurality of active semiconductor devices formed on a device side of said first chip, and said second chip includes a front side on which a plurality of second semiconductor devices is formed and a grind side opposite to said front side, wherein
said plurality of second semiconductor devices include active and passive semiconductor devices.
15. The 3D integrated circuit of claim 14 wherein said second chip includes a denuded zone in which said plurality of second semiconductor devices is formed.