Elemental semiconductor material contact for high electron mobility transistor
View Patent ↗Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.
1. A method of forming a semiconductor structure comprising:
providing a substrate including a vertical stack of a substrate compound semiconductor layer and a top compound semiconductor layer;
forming a gate electrode on a horizontal surface of a portion of said top compound semiconductor layer;
forming a source-side trench and a drain-side trench in said substrate employing said gate electrode as an etch mask;
forming a source region and a drain region by selectively depositing at least one elemental semiconductor material in said source-side trench and said drain-side trench;
forming a dielectric material layer over said top surface of said top compound semiconductor layer; and
forming a hole through said dielectric material layer, wherein a portion of said top surface of said top compound semiconductor layer is physically exposed within said hole, and wherein said gate electrode is formed by deposition of a metallic material in, and above, said hole.
2. The method of claim 1 , wherein said substrate compound semiconductor layer comprise a first single crystalline compound semiconductor material and said top compound semiconductor layer comprises a second single crystalline compound semiconductor material having a greater charge carrier mobility than said first single crystalline compound semiconductor material.
3. The method of claim 2 , wherein said at least one elemental semiconductor material is deposited by selective epitaxy with epitaxial alignment with said second single crystalline compound semiconductor material.
4. The method of claim 1 , wherein said source-side trench and said drain-side trench extend below a horizontal plane including an interface between said top compound semiconductor layer and said substrate compound semiconductor layer.
5. The method of claim 1 , wherein said source region and said drain region consist essentially of said at least one semiconductor material, hydrogen atoms, and electrical dopant atoms.
6. The method of claim 1 , wherein each of said source region and said drain region comprises a single crystalline or polycrystalline silicon material, a single crystalline or polycrystalline germanium material, or a single crystalline or polycrystalline alloy of silicon and germanium.
7. The method of claim 1 , further comprising:
forming a source-side metal-semiconductor alloy portion directly on a top surface of said source region; and
forming a drain-side metal-semiconductor alloy portion directly on a top surface of said drain region.
8. The method of claim 1 , further comprising:
forming a template material layer including an opening, wherein said template material layer is formed over said dielectric material layer prior to, or after, forming said hole in said dielectric material layer, and said opening overlies an entirety of said hole;
removing said template material layer selective to said dielectric material layer; and
patterning said dielectric material layer by an anisotropic etch employing said gate electrode as an etch mask.
9. The method of claim 8 , further comprising forming a fluorine-doped region within a portion of said top compound semiconductor layer underlying said hole.