Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure
View Patent ↗Disclosed are embodiments of a structure having a metal layer with top surface and sidewall passivation and a method of forming the structure. In one embodiment, a metal layer is electroplated onto a portion of a seed layer at the bottom of a trench. Then, the sidewalls of the metal layer are exposed and, for passivation, a second metal layer is electroplated onto the top surface and sidewalls of the metal layer. In another embodiment, a trench is formed in a dielectric layer. A seed layer is formed over the dielectric layer, lining the trench. A metal layer is electroplated onto the portion of the seed layer within the trench and a second metal layer is electroplated onto the top surface of the metal layer. Thus, in this case, passivation of the top surface and sidewalls of the metal layer is provided by the second metal layer and the dielectric layer, respectively.
1. A method of forming an integrated circuit structure incorporating a back end of the line (BEOL) redistribution layer with top surface and sidewall passivation provided by metal, said method comprising:
forming a seed layer on a substrate;
forming a mask layer on said seed layer;
forming a trench extending through said mask layer to said seed layer and having first sidewalls;
forming spacers within said trench on said seed layer and positioned laterally adjacent to said first sidewalls such that a first portion of said seed layer remains exposed;
forming a first metal layer for said redistribution layer on said first portion of said seed layer;
after said forming of said first metal layer, removing said spacers so as to expose second sidewalls of said first metal layer and second portions of said seed layer adjacent to said second sidewalls;
forming, for said top surface and sidewall passivation of said redistribution layer, a second metal layer on said second portions of said seed layer, said second sidewalls of said first metal layer and on a top surface of said first metal layer, said second metal layer comprising a different metal material than said first metal layer and said forming of said second metal layer comprising performing a selective electroplating process;
removing said mask layer to expose third portions of said seed layer adjacent to said second portions; and
performing an etch process to remove said third portions in order to complete said redistribution layer with said top surface and sidewall passivation; and
forming a blanket polymide layer over said second metal layer and exposed portions of said substrate following removal of said third portions.
2. The method of claim 1 ,
said forming of said seed layer comprising forming a copper seed layer by physical vapor deposition, and
said forming of said first metal layer comprising electroplating a copper layer onto said copper seed layer.
3. The method of claim 1 , said forming of said second metal layer comprising electroplating, onto said first metal layer, any of a gold layer, a nickel layer, a cobalt layer, a nickel boride layer, a nickel phosphide layer, a cobalt boride layer and a cobalt phosphide layer.
4. The method of claim 1 , further comprising:
before said forming of said seed layer:
forming a conductive pad on said substrate;
forming a first dielectric layer on said substrate and said conductive pad;
forming an opening through said first dielectric layer to expose said conductive pad such that, after said forming of said seed layer, said seed layer lines said opening; and,
after completing said redistribution layer with said top surface and sidewall passivation, forming a solder ball on said redistribution layer such that said redistribution layer electrically connects said solder ball to said conductive pad.
5. The method of claim 1 , further comprising:
before said forming of said seed layer, forming a barrier layer, said forming of said seed layer comprising forming said seed layer on said barrier layer.
6. A method of forming an integrated circuit structure incorporating a back end of the line (BEOL) redistribution layer with top surface and sidewall passivation provided by metal, said method comprising:
forming a seed layer on a dielectric layer, said dielectric layer having discrete openings extending vertically to two conductive pads and said seed layer lining said openings;
forming a mask layer on said seed layer;
forming a trench extending through said mask layer to said seed layer and having first sidewalls;
forming spacers within said trench on said seed layer and positioned laterally adjacent to said first sidewalls such that a first portion of said seed layer remains exposed;
forming a first metal layer for said redistribution layer on said first portion of said seed layer;
after said forming of said first metal layer, removing said spacers so as to expose second sidewalls of said first metal layer and second portions of said seed layer adjacent to said second sidewalls;
forming, for said top surface and sidewall passivation of said redistribution layer, a second metal layer on said second portions of said seed layer, said second sidewalls of said first metal layer and on a top surface of said first metal layer, said second metal layer comprising a different metal material than said first metal layer and said forming of said second metal layer comprising forming said second metal layer by performing a selective electroplating process;
removing said mask layer to expose third portions of said seed layer adjacent to said second portions;
performing an etch process to remove said third portions in order to complete said redistribution layer with said top surface and sidewall passivation such that said redistribution layer electrically connects said two conductive pads; and
forming a blanket polymide layer over said second metal layer and exposed portions of said dielectric layer following removal of said third portions.
7. The method of claim 6 ,
said forming of said seed layer comprising forming a copper seed layer by physical vapor deposition, and
said forming of said first metal layer comprising electroplating a copper layer onto said copper seed layer.
8. The method of claim 6 , said forming of said second metal layer comprising electroplating, onto said first metal layer, any of a gold layer, a nickel layer, a cobalt layer, a nickel boride layer, a nickel phosphide layer, a cobalt boride layer and a cobalt phosphide layer.
9. The method of claim 6 , further comprising:
before said forming of said seed layer, forming a barrier layer, said forming of said seed layer comprising forming said seed layer on said barrier layer.