Method and structure for finFET with finely controlled device width
View Patent ↗A structure and method for fabricating finFETs of varying effective device widths is disclosed. Groups of fins are shortened by a predetermined amount to achieve an effective device width that is equivalent to a real (non-integer) number of full-sized fins. The bottom of each group of fins is coplanar, while the tops of the fins from the different groups of fins may be at different levels.
1. A method for forming a semiconductor structure comprising:
covering a first group of fins disposed on a semiconductor substrate with a mask layer;
removing an upper portion of a second group of fins disposed on the semiconductor substrate, such that the first group of fins is coplanar with the second group of fins on the semiconductor substrate;
removing the mask layer;
forming a first finFET, wherein a first replacement metal gate of the first finFET comprises the first group of fins; and
forming a second finFET, wherein a second replacement metal gate of the second finFET comprises the second group of fins; and further comprising:
computing a fin height reduction value; and
wherein removing an upper portion of a second group of fins disposed on the semiconductor substrate comprises removing an amount of fin material from the second group of fins that corresponds to the fin height reduction value; and further comprising:
establishing an effective fin count parameter as a non-integer number of fins;
computing a reduced perimeter value based on the effective fin count parameter; and
wherein computing the fin height reduction value comprises determining a height for the second group of fins based on the reduced perimeter value.
2. The method of claim 1 , wherein removing an upper portion of a second group of fins is performed via a reactive ion etch process.
3. The method of claim 1 , wherein computing a fin height reduction value comprises computing a fin height reduction value ranging from 10 to 30 percent of the height of the first group of fins.
4. The method of claim 1 , wherein computing a fin height reduction value comprises computing a fin height reduction value ranging from 20 to 60 nanometers.
5. A method for forming a semiconductor structure comprising:
covering a first group of fins and a second group of fins disposed on a semiconductor substrate with a first mask layer;
removing an upper portion of a third group of fins disposed on the semiconductor substrate, such that the first group of fins, second group of fins, and third group of fins are coplanar with each other on the semiconductor substrate;
removing the first mask layer;
covering the first group of fins and the third group of fins with a second mask layer;
removing an upper portion of the second group of fins disposed on the semiconductor substrate, such that the first group of fins, second group of fins, and third group of fins are coplanar with each other on the semiconductor substrate;
removing the second mask layer;
forming a first finFET, wherein a first replacement metal gate of the first finFET comprises the first group of fins;
forming a second finFET, wherein a second replacement metal gate of the second finFET comprises the second group of fins; and
forming a third finFET, wherein a third replacement metal gate of the third finFET comprises the third group of fins; and further comprising:
computing a fin height reduction value; and
wherein removing an upper portion of a second group of fins disposed on the semiconductor substrate comprises removing an amount of fin material from the second group of fins that corresponds to the fin height reduction value; and further comprising:
establishing an effective fin count parameter as a non-integer number of fins;
computing a reduced perimeter value based on the effective fin count parameter;
wherein computing the fin height reduction value comprises determining a height for the second group of fins based on the reduced perimeter value.
6. The method of claim 5 , wherein removing an upper portion of the second group of fins and removing an upper portion of the third group of fins is performed via a reactive ion etch process.
7. The method of claim 5 , wherein computing a fin height reduction value comprises computing a fin height reduction value ranging from 10 to 30 percent of the fin height of the first group of fins.
8. The method of claim 5 , wherein computing a fin height reduction value comprises computing a fin height reduction value ranging from 20 to 60 nanometers.