Integrated circuits with protected resistors and methods for fabricating the same

1. A method of producing an integrated circuit comprising:

depositing a first dielectric layer over a resistor and a transistor of the integrated circuit;

depositing an amorphous silicon layer over the first dielectric layer;

implanting the amorphous silicon layer over the resistor to create an etch mask;

removing the amorphous silicon layer and the first dielectric layer overlying the transistor while leaving the etch mask over the resistor; and

siliciding a contact location on the transistor.

2. The method of claim 1 wherein implanting the amorphous silicon layer further comprises implanting carbon into the amorphous silicon layer to produce the etch mask comprising carbon doped amorphous silicon.

3. The method of claim 1 wherein siliciding the contact location further comprises depositing a metal on the contact location and thermally annealing the contact location.

4. The method of claim 3 wherein depositing the metal further comprises depositing the metal comprising nickel on the contact location.

5. The method of claim 1 wherein depositing the first dielectric layer over the resistor and the transistor further comprises depositing silicon oxide over the resistor and the transistor.

6. The method of claim 1 wherein implanting the amorphous silicon layer to create the etch mask further comprises:

depositing an etch mask photoresist over the transistor and the resistor;

patterning the etch mask photoresist; and

removing the etch mask photoresist over the resistor while leaving the etch mask photoresist over the transistor.

7. The method of claim 1 further comprising forming a contact to the contact location after siliciding the contact location.

8. A method of producing an integrated circuit comprising:

protecting a resistor of the integrated circuit with a first dielectric layer and an etch mask, wherein the first dielectric layer is positioned between the resistor and the etch mask, wherein the etch mask has an etch mask thickness of no more than about 200 angstroms, and wherein creating the etch mask comprises implanting an implant material into an amorphous silicon layer;

exposing a transistor of the integrated circuit, wherein exposing the transistor comprises removing the amorphous silicon layer from over the transistor while the etch mask remains over the resistor; and

siliciding a contact location on the transistor.

9. The method of claim 8 wherein protecting the resistor further comprises:

depositing the first dielectric layer over the resistor; and

depositing the amorphous silicon layer over the first dielectric layer.

10. The method of claim 9 wherein implanting the implant material further comprises implanting carbon into the amorphous silicon layer to produce the etch mask comprising carbon doped amorphous silicon.

11. The method of claim 8 wherein exposing the transistor further comprises removing an etch mask photoresist, and the first dielectric layer from over the transistor.

12. The method of claim 8 wherein siliciding the contact location further comprises depositing a metal over the contact location, and annealing the contact location.

13. The method of claim 12 wherein depositing the metal over the contact location further comprises depositing the metal comprising nickel over the contact location.

14. The method of claim 8 wherein protecting the resistor further comprises depositing the first dielectric layer comprising silicon oxide over the resistor.

15. The method of claim 8 further comprising forming a contact to the contact location after siliciding the contact location.