Transistor formation using cold welding
View Patent ↗A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.
1. A semiconductor device, comprising:
a first semiconductor substrate having a first metal layer formed directly on a major surface of the first semiconductor substrate;
a second semiconductor substrate having a second metal layer formed directly on a major surface of the second substrate; and
a cold weld interface coupling the second metal layer to the first metal layer that provides at least one of a heat sink or ground plane structure, at least one of the first metal layer and the second metal layer of the heat sink or ground plane structure having sidewalls that are aligned with sidewalls of a source region and a drain region of the semiconductor device formed in at least one of the first semiconductor substrate and the second semiconductor substrate.
2. The device as recited in claim 1 , wherein at least one of the first metal layer and the second metal layer includes a textured three-dimensional surface.
3. The device as recited in claim 1 , wherein the first semiconductor substrate includes a semiconductor component.
4. The device as recited in claim 1 , wherein the first metal layer and the second metal layer include a same metal material.
5. The device as recited in claim 1 , wherein the first metal layer and the second metal layer include different metal materials.
6. The device as recited in claim 1 , wherein the second semiconductor substrate is a flexible material.
7. A semiconductor device, comprising:
a substrate;
a first metal layer formed directly over the substrate;
a cold weld interface coupling a second metal layer to the first metal layer;
a dielectric layer on which the second metal layer is formed;
a monocrystalline channel layer on which the dielectric layer is formed, the channel layer including source and drain regions therein; and
a gate structure formed over the channel layer, wherein the cold weld interface connects one or more transistor devices to the substrate, and the cold weld interface coupling the second metal layer to the first metal layer to provide at least one of a heat sink or ground plane structure, at least one of the first metal layer and the second metal layer of the heat sink or ground plane structure having sidewalls that are aligned with sidewalls of the source region and the drain region.
8. The device as recited in claim 7 , further comprising a diffusion barrier formed between the channel layer and the second metal layer.
9. The device as recited in claim 7 , wherein the channel layer includes a III-V semiconductor material.
10. The device as recited in claim 7 , wherein the substrate includes semiconductor components.
11. The device as recited in claim 7 , wherein the first metal layer and the second metal layer include a same metal material.
12. The device as recited in claim 7 , wherein the first metal layer and the second metal layer include different metal materials.
13. The device as recited in claim 7 , wherein at least one of the first metal layer and the second metal layer include a textured three-dimensional surface.
14. The device as recited in claim 7 , wherein the substrate includes one of a flexible material and a metallic material.
15. A semiconductor device, comprising:
a silicon substrate;
a first metal layer formed directly over the substrate;
a cold weld interface coupling a second metal layer to the first metal layer;
a dielectric layer on which the second metal layer is formed;
a monocrystalline III-V semiconductor channel layer on which the dielectric layer is formed, the channel layer including source and drain regions therein; and
a gate structure formed over the channel layer, wherein the cold weld interface connects one or more transistor devices to the substrate, and the cold weld interface coupling the second metal layer to the first metal layer to provide at least one of a heat sink or ground plane structure, at least one of the first metal layer and the second metal layer of the heat sink or ground plane structure having sidewalls that are aligned with sidewalls of the source region and the drain region.
16. The device as recited in claim 15 , further comprising a diffusion barrier formed between the channel layer and the second metal layer.
17. The device as recited in claim 15 , wherein the channel layer forms a III-V semiconductor device and further comprising semiconductor devices formed in the silicon substrate.
18. The device as recited in claim 15 , wherein the first metal layer and the second metal layer include a same metal material.
19. The device as recited in claim 15 , wherein the first metal layer and the second metal layer include different metal materials.
20. The device as recited in claim 15 , wherein at least one of the first metal layer and the second metal layer include a textured three-dimensional surface.