Devices with gate-to-gate isolation structures and methods of manufacture

1. A method, comprising:

forming a plurality of isolation structures in a pad film and an underlying substrate, such that each separate isolation structure is formed by filling a separate trench;

completely protecting one of the plurality of isolation structures filled in the trench in order to preserve its height;

removing portions of unprotected isolation structures such that the unprotected isolation structures are of a different height than the one of the plurality isolation structures;

removing the pad film and protection over the one of the plurality isolation structures, wherein the one of the plurality of isolation structures extends above the underlying substrate; and

forming at least one gate electrode on the substrate, over the unprotected isolation structures and abutting sides of the one of the plurality of isolation structures.

2. The method of claim 1 , wherein the substrate is a BULK wafer.

3. The method of claim 1 , wherein the substrate is a Silicon on Insulator (SOI), and the plurality of isolation structures are formed by etching the trenches to an insulator layer of the SOI and filling the trenches with insulator material.

4. The method of claim 1 , wherein the pad film is deposited on the underlying substrate.

5. The method of claim 4 , wherein the pad film is a stack SiO 2 and Si 3 N 4 .

6. The method of claim 1 , wherein the plurality of isolation structures are formed in trenches having a width of about 20 nm.

7. The method of claim 6 , wherein the trenches are formed to have uniform spacing therebetween in a regular pattern.

8. The method of claim 1 , wherein the one of the plurality of isolation structures provides a physical and electrical isolation between adjacent gate electrodes.

9. The method of claim 1 , wherein the one of the plurality of isolation structures has a width of about 20 nm.

10. The method of claim 1 , wherein the protection is formed by a mask layer formed over the one of the plurality of isolation structures.

11. The method of claim 1 , wherein the one of the plurality of isolation structures is at a sufficient height to isolate adjacent gate electrodes at a minimum image spacing.

12. The method of claim 1 , wherein the removing portions of the unprotected isolation structures forms a stepped structure, with the unprotected isolation structures being lower than the one of the plurality of isolation structures with respect to a surface of the underlying substrate.

13. A method comprising:

forming a pad film on a substrate;

etching the pad film and substrate to form a plurality of trenches;

filling the trenches with insulator material to form a plurality of an isolation structure within each of the trenches;

completely protecting one of the filled trenches with a mask to form a central isolation structure;

removing the pad film and portions of surrounding isolation structures which are unprotected such that the surrounding isolation structures are of a different height than the central isolation structure;

removing the mask and any remaining pad film, while a portion of the central isolation structure remains extended above the substrate; and

forming at least one electrode stack on the substrate, over the surrounding isolation structures and abutting sides of the central isolation structure that remained completely protected,

wherein the central isolation structure provides a physical and electrical isolation between adjacent electrode stacks.

14. The method of claim 13 , wherein the substrate is BULK silicon.

15. The method of claim 13 , wherein the substrate is a Silicon on Insulator (SOI), and the plurality of trenches extend to an insulator layer of the SOI.

16. The method of claim 13 , wherein the at least one electrode stack comprises polysilicon or stack of metal and polysilicon formed on a gate dielectric.

17. The method of claim 13 , wherein the at least one electrode stack buries the surrounding isolation structures.

18. The method of claim 13 , wherein the central isolation structure has a width of about 20 nm.

19. The method of claim 13 , wherein the central isolation structure is at a sufficient height to isolate the adjacent electrode stacks at a minimum image spacing.

20. A structure, comprising:

a first plurality of isolation regions formed in a substrate;

a second plurality of isolation regions formed in the substrate and extending to a height higher than the first plurality of isolation regions with respect to a surface of the substrate, wherein each of the second plurality of isolation regions comprise a respective completely filled trench; and

gate stack regions overlying the first plurality of isolation regions and physically and electrically isolated from one another by the second plurality of isolation regions, wherein the gate stack regions abut against non-etched sides of the second plurality of isolation regions.

21. The method of claim 1 , wherein the protecting one of the plurality of isolation structures completely covers the one of the plurality of isolation structures.

22. The method of claim 21 , wherein the at least one gate electrode is formed directly on the substrate.

23. The method of claim 13 , wherein the protecting the central isolation structure with a mask completely covers all portions of the central isolation structure.

24. The method of claim 13 , wherein the at least one electrode stack is formed directly on the substrate.

25. The structure of claim 20 , wherein the gate stack regions are formed in direct contact with exposed portions of the substrate.