Integrated planar and multiple gate FETs
View Patent ↗A multiple gate field effect transistor and a planar field effect transistor formed in the same substrate each have a top planar surface underneath each corresponding gate that are co-planar with one another and also co-planar with a top surface of a shallow trench isolation region located therebetween. The relatively older planar FET fabrication technology has added to it the relatively newer MUGFET fabrication technology without disruption to the planar fabrication technology and with relatively little added cost.
1. A method of fabricating a planar field effect transistor (FET) and a multiple gate FET (MUGFET) together in a multiple layer substrate, comprising:
etching an upper layer in the substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET;
filling etched regions in the upper layer of the substrate with a shallow trench isolation (STI) material to form a plurality of STI filled regions;
forming a plurality of trenches in the first active device region;
forming a first gate region for the MUGFET over a portion of the first active device region; and
forming a second gate region for the planar FET over a portion of the pair of second active device regions, wherein forming a first gate region for the MUGFET over a portion of the first active device region and forming a second gate region for the planar FET over a portion of the pair of second active device regions comprises forming a dielectric layer on top of the upper layer in the substrate, forming a gate layer on top of the dielectric layer, and etching the gate layer and the dielectric layer at selective locations to form the first and second gate regions; and
wherein top surfaces of each of the STI filled regions, the first active device region for the MUGFET, the plurality of trenches in the first active device region, and the second active device regions are all co-planar with respect to one another.
2. The method of claim 1 , wherein the upper layer in the substrate comprises silicon.
3. The method of claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate having a lower layer of silicon, a layer of insulator disposed on top of the lower layer of silicon, and the upper layer comprises silicon.
4. The method of claim 1 , wherein filling etched regions in the upper layer of the substrate with an STI material fills the etched regions with the STI material to a level that is the same as that of the first active region and the pair of second active regions.
5. The method of claim 1 , wherein forming a plurality of trenches in the first active device region comprises selectively etching portions of the first active device region to remove the material of the first active device region, wherein the plurality of trenches in the first active device region comprises channels for the MUGFET.
6. The method of claim 1 , further comprising forming at least one oxide pad film layer on top of the upper layer in the substrate prior to etching an upper layer in the substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET.
7. The method of claim 6 , wherein after filling etched regions in the upper layer of the substrate with an STI material, removing the at least one oxide pad film layer.
8. A method of fabricating a planar field effect transistor (FET) and a multiple gate FET (MUGFET) together in a multiple layer substrate, comprising:
forming at least one oxide pad film layer on top of an upper layer in the substrate;
etching the at least one oxide pad film layer and the upper layer in the substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET;
filling etched regions in the upper layer of the substrate with a shallow trench isolation (STI) material to form a plurality of STI filled regions;
polishing the filled STI regions, the first active device region and the pair of second active device regions, the polishing including removing the at least one oxide pad film layer;
forming a plurality of trenches in the first active device region;
forming a first gate region for the MUGFET over a portion of the first active device region;
forming a second gate region for the planar FET over a portion of the pair of second active device regions;
wherein top surfaces of each of the STI filled regions, the first active device region for the MUGFET, the plurality of trenches in the first active device region, and the second active device regions are all co-planar with respect one another.
9. The method of claim 8 , wherein the step of polishing comprises a chemical mechanical polishing step.
10. A method of fabricating a planar field effect transistor (FET) and a multiple gate FET (MUGFET) together in a silicon-on-insulator (SOI) substrate, comprising:
removing selected portions of an upper silicon layer in the SOI substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET;
filling the removed selected portions in the upper silicon layer of the SOI substrate with a shallow trench isolation (STI) material to form a plurality of STI filled regions;
forming a plurality of trenches in the first active device region;
forming a first gate region for the MUGFET over a portion of the first active device region; and
forming a second gate region for the planar FET over a portion of the pair of second active device regions, wherein forming a first gate region for the MUGFET over a portion of the first active device region and forming a second gate region for the planar FET over a portion of the pair of second active device regions comprises forming a dielectric layer on top of the upper silicon layer in the SOI substrate, forming a gate layer on top of the dielectric layer, and etching the gate layer and the dielectric layer at selective locations to form the first and second gate regions; and
wherein top surfaces of each of the STI filled regions, the first active device region for the MUGFET, the plurality of trenches in the first active device region, and the second active device regions are all co-planar with respect to one another.
11. The method of claim 10 , wherein removing selected portions of an upper silicon layer in the SOI substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET comprises etching selected portions of the upper silicon layer in the SOI substrate.
12. The method of claim 10 , wherein filling etched regions in the upper layer of the substrate with an STI material fills the etched regions with the STI material to a level that is the same as that of the first active region and the pair of second active regions.
13. The method of claim 10 , wherein forming a plurality of trenches in the first active device region comprises selectively etching portions of the first active device region to remove the material of the first active device region, wherein the plurality of trenches in the first active device region comprises channels for the MUGFET.
14. The method of claim 10 , further comprising forming at least one oxide pad film layer on top of the upper silicon layer in the SOI substrate prior to etching an upper silicon layer in the SOI substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET.
15. A method of fabricating a planar field effect transistor (FET) and a multiple gate FET (MUGFET) together in a silicon-on-insulator (SOI) substrate, comprising:
forming at least one oxide pad film layer on top of an upper silicon layer in the SOI substrate;
removing selected portions of the upper silicon layer in the SOI substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET;
filling the removed selected portions in the upper silicon layer of the SOI substrate with a shallow trench isolation (STI) material to form a plurality of STI filled regions;
polishing the filled STI regions, the first active device region and the pair of second active device regions, the polishing including removing the at least one oxide pad film layer;
forming a plurality of trenches in the first active device region;
forming a first gate region for the MUGFET over a portion of the first active device region; and
forming a second gate region for the planar FET over a portion of the pair of second active device regions;
wherein top surfaces of each of the STI filled regions, the first active device region for the MUGFET, the plurality of trenches in the first active device region, and the second active device regions are all co-planar with respect to one another.
16. A method of fabricating a planar field effect transistor (FET) and a multiple gate FET (MUGFET) together in a silicon-on-insulator (SOI) substrate, comprising:
etching selected portions of an upper silicon layer in the SOI substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET;
filling the removed selected portions in the upper silicon layer of the SOI substrate with a shallow trench isolation (STI) material to form a plurality of STI filled regions;
forming a plurality of trenches in the first active device region;
forming a dielectric layer on top of the upper silicon layer in the SOI substrate;
forming a gate layer on top of the dielectric layer; and
etching the gate layer and the dielectric layer at selective locations to form a first gate region for the MUGFET over a portion of the first active device region and a second gate region for the planar FET over a portion of the pair of second active device regions;
wherein top surfaces of each of the STI filled regions, the first active device region for the MUGFET, the plurality of trenches in the first active device region, and the second active device regions are all co-planar with respect to one another.
17. The method of claim 16 , wherein forming a plurality of trenches in the first active device region comprises selectively etching portions of the first active device region to remove the material of the first active device region, wherein the plurality of trenches in the first active device region comprises channels for the MUGFET.
18. The method of claim 16 , further comprising forming at least one oxide pad film layer on top of the upper silicon layer in the SOI substrate prior to etching an upper silicon layer in the SOI substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET, and wherein after filling the etched regions in the upper silicon layer of the SOI substrate with an STI material, removing the at least one oxide pad film layer and polishing the filled STI regions, the first active device region and the pair of second active device regions.