Electronic fuse with resistive heater

1. A method of forming an electronic fuse, the method comprising:

forming an M x level comprising a first M x metal, and a second M x metal;

forming a first M x+1 dielectric above the M x level;

forming a conductive path on a portion of the first M x+1 dielectric above the first M x metal and above the second M x metal;

forming a second M x+1 dielectric above the first M x+1 dielectric and above the conductive path, wherein the first M x+1 dielectric and the second M x+1 dielectric together form an M x+1 level;

forming a first via and a second via in the M x+1 level, the conductive path extending from the first via to the second via and partially encircling the first via; and

forming a first M x+1 metal and a second M x+1 metal in the M x+1 level, the first via extending vertically and electrically connecting the first M x metal to the first M x+1 metal, and the second via extending vertically and electrically connecting the second M x metal to the second M x+1 metal.

2. The method of claim 1 , wherein forming the conductive path on the portion of the first M x+1 dielectric above the first M x metal and above the second M x metal comprises:

forming the conductive path within a distance ranging from about 100 nm to about 300 nm of the first via.

3. The method of claim 1 , wherein forming the conductive path on the portion of the first M x+1 dielectric above the first M x metal and above the second M x metal comprises:

forming the conductive path comprising a width ranging from about 20 nm to about 40 nm.

4. The method of claim 1 , wherein forming the conductive path on the portion of the first M x+1 dielectric above the first M x metal and above the second M x metal comprises:

forming the conductive path comprising a thickness ranging from about 2 nm to about 5 nm.

5. The method of claim 1 , wherein forming the conductive path on the portion of the first M x+1 dielectric above the first M x metal and above the second M x metal comprises:

depositing a conductive layer comprising a thickness ranging from about 2 nm to about 5 nm; and

removing a portion of the conductive layer to form the conductive path.

6. The method of claim 1 , wherein forming the conductive path on the portion of the first M x+1 dielectric above the first M x metal and above the second M x metal comprises:

depositing a metal having a different etch rate than the first M x+1 dielectric under the same etch conditions.

7. The method of claim 1 , wherein forming the first via and the second via in the M x+1 level comprises:

forming the first and second vias comprising a width ranging from about 10 nm to about 40 nm.

8. The method of claim 1 , wherein forming the first via and the second via in the M x+1 level comprises:

forming a damaged region comprising an undercut feature and poor liner coverage.

9. The method of claim 1 , further comprising:

applying a programming current from the second M x metal to the first M x+1 metal through the conductive path.

10. A method of forming an electronic fuse, the method comprising:

forming an M x level comprising a first M x metal, and a second M x metal;

forming a first M x+1 dielectric above the M x level;

forming a conductive layer on top of the first M x+1 dielectric above the first M x metal and above the second M x metal;

forming a conductive path on a portion of the first M x+1 dielectric above the first M x metal and above the second M x metal by patterning the conductive layer;

forming a second M x+1 dielectric above the first M x+1 dielectric and above the conductive path, wherein the first M x+1 dielectric and the second M x+1 dielectric together form an M x+1 level;

forming a first via and a second via in the M x+1 level, the conductive path extending from the first via to the second via and partially encircling the first via; and

forming a first M x+1 metal and a second M x+1 metal in the M x+1 level, the first via extending vertically and electrically connecting the first M x metal to the first M x+1 metal, and the second via extending vertically and electrically connecting the second M x metal to the second M x+1 metal.

11. The method of claim 10 , wherein forming the conductive path on the portion of the first M x+1 dielectric above the first M x metal and above the second M x metal comprises:

forming the conductive path within a distance ranging from about 100 nm to about 300 nm of the first via.

12. The method of claim 10 , wherein forming the conductive path on the portion of the first M x+1 dielectric above the first M x metal and above the second M x metal comprises:

forming the conductive path comprising a width ranging from about 20 nm to about 40 nm.

13. The method of claim 10 , wherein forming the conductive path on the portion of the first M x+1 dielectric above the first M x metal and above the second M x metal comprises:

forming the conductive path comprising a thickness ranging from about 2 nm to about 5 nm.

14. The method of claim 10 , wherein forming the conductive path on the portion of the first M x+1 dielectric above the first M x metal and above the second M x metal comprises:

depositing a metal having a different etch rate than the first M x+1 dielectric under the same etch conditions.

15. The method of claim 10 , wherein forming the first via and the second via in the M x+1 level, the conductive path extending from the first via to the second via and partially encircling the first via comprises:

forming the first and second vias comprising a width ranging from about 10 nm to about 40 nm.

16. The method of claim 10 , wherein forming the first via and the second via in the M x+1 level comprises:

forming a damaged region comprising an undercut feature and poor liner coverage.

17. The method of claim 10 , further comprising:

applying a programming current from the second M x metal to the first M x+1 metal through the conductive path.