Integrated circuits having backside test structures and methods for the fabrication thereof

1. A method for fabricating an integrated circuit, the method comprising the steps of:

providing a semiconductor substrate having a frontside and a backside;

forming semiconductor devices on the frontside of the semiconductor substrate;

forming at least one blind via extending into the frontside and terminating in the semiconductor substrate;

thinning the semiconductor substrate to reposition the backside, wherein the repositioned backside intersects the at least one blind via to form at least one Through-Silicon-Via (TSV) through the semiconductor substrate;

forming a recess in the repositioned backside of the semiconductor substrate adjacent the at least one TSV;

forming a backside probe pad over the backside of the semiconductor substrate and electrically coupled to the at least one TSV; and

forming a frontside bondpad over the frontside of the semiconductor substrate and electrically coupled to the backside probe pad by the at least one TSV.

2. A method according to claim 1 wherein the step of forming a backside probe pad comprises forming the backside probe pad over and in electrical contact with the at least one TSV.

3. A method according to claim 1 wherein the step of forming a backside probe pad comprises depositing an electrically conductive material over the backside of the semiconductor substrate having a hardness greater than that of copper.

4. A method according to claim 3 wherein the step of depositing comprises depositing a metal selected from the group consisting of nickel, tungsten, cobalt, molybdenum, and tantalum.

5. A method according to claim 1 wherein the at least one blind via is at least as long as the at least one TSV.

6. A method according to claim 1 wherein the step of forming a backside probe pad comprises forming the backside probe pad at a location substantially aligned with the frontside bondpad, as taken along an axis substantially orthogonal to a major frontside surface of the semiconductor substrate.

7. A method according to claim 1 wherein the step of thinning the semiconductor substrate to reposition the backside forms a plurality of TSVs through the semiconductor substrate and extending from the frontside bondpad to the backside probe pad.

8. A method according to claim 1 wherein the step of forming a backside probe pad comprises forming a backside probe pad completely within the recess.

9. A method according to claim 1 wherein the step of forming a recess in the repositioned backside of the semiconductor substrate comprises exposing a portion of the repositioned backside of the semiconductor substrate to an etchant having a crystal plane selective chemistry.

10. A method according to claim 9 wherein the step of exposing comprises exposing a portion of the repositioned backside of the semiconductor substrate to an etchant having a potassium hydroxide chemistry.

11. A method for fabricating an integrated circuit having a backside test structure, the method comprising the steps of:

providing a semiconductor substrate having a frontside and a backside;

forming a plurality of blind vias extending from the frontside and terminating in the semiconductor substrate;

removing a portion of the semiconductor substrate to expose the plurality of blind vias and form a plurality of Through-Silicon-Vias (TSVs) extending from the frontside to the backside of the semiconductor substrate, wherein each blind via is at least as long as each TSV, wherein removing the portion of the semiconductor substrate comprises thinning the semiconductor substrate to reposition the backside, and wherein the repositioned backside intersects the plurality of blind vias to form the plurality of TSVs extending from the frontside to the repositioned backside of the semiconductor substrate;

etching a recess in the repositioned backside of the semiconductor substrate adjacent the plurality of TSVs therethrough;

forming a backside probe pad over the backside of the semiconductor substrate and in electrical contact with the plurality of TSVs; and

forming a frontside bondpad over the frontside of the semiconductor substrate and electrically coupled to the backside probe pad by the plurality of TSVs.

12. A method according to claim 11 wherein the step of etching comprises subjecting the portion of the repositioned backside of the semiconductor substrate adjacent the plurality of TSVs to an etchant having a crystal plane selective chemistry.

13. A method according to claim 11 wherein the step of forming the backside probe pad comprises depositing a metal into the recess to form the backside probe pad completely within the recess.

14. A method according to claim 13 wherein the metal is selected from the group consisting of nickel and tungsten.

15. An integrated circuit, comprising:

a semiconductor substrate having a frontside and a backside, wherein the substrate is formed with a recess in the backside;

a backside probe pad formed completely within the recess in the backside such that the recess is deeper than the backside probe pad;

a frontside bondpad formed over the frontside of the semiconductor substrate; and

at least one Through-Silicon-Via (TSV) extending through the semiconductor substrate and electrically coupling the backside probe pad to the frontside bondpad; and

semiconductor devices formed on the frontside of the semiconductor substrate.

16. An integrated circuit according to claim 15 wherein the backside probe pad is substantially aligned with frontside bondpad, as taken along an axis substantially orthogonal to a major backside surface of the integrated circuit, and wherein the at least one TSV extends from the frontside bondpad, through the semiconductor substrate, and to the backside probe pad.