Structure and method to create stress trench
View Patent ↗An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.
1. An integrated circuit (IC) chip comprising:
a junction gate field-effect transistor (JFET) having a top gate, a bottom gate, and a channel region therebetween;
a trench, adjacent to the JFET, wherein the trench includes a stress-inducing material therein which imparts a horizontal stress on the channel region of the JFET, and wherein the trench extends deeper into the chip than the JFET.
2. The IC chip of claim 1 , wherein the trench comprises a pair of trenches, each trench adjacent to the JFET.
3. The IC chip of claim 1 , wherein the trench is disposed substantially perpendicular to a direction of electric current flow through the channel region of the JFET.
4. The IC chip of claim 1 , wherein the stress-inducing material comprises a silicon nitride stress liner.
5. The IC chip of claim 1 , wherein the stress-inducing material is substantially flush with a top surface of the IC chip.
6. The IC chip of claim 1 , wherein the stress-inducing material imparts a compressive stress in the case that the channel region of the JFET includes p-type dopants, and the stress-inducing material imparts a tensile stress in the case that the channel region of the JFET includes n-type dopants.
7. The IC chip of claim 1 , wherein the stress inducing material substantially fills the trench.
8. The IC chip of claim 1 , wherein the horizontal stress imparted on the channel region of the JFET is at least approximately 1 GPa.
9. A method of imparting a stress onto a junction gate field-effect transistor (JFET) having a top gate, a bottom gate, and a channel region therebetween in an integrated circuit (IC) chip, the method comprising:
creating a trench adjacent to the JFET, wherein the trench extends deeper into the chip than the JFET; and
at least partially filling the trench with a stress-inducing material which imparts a horizontal stress on the channel region of the JFET.
10. The method of claim 9 , wherein the creating includes creating a pair of trenches, each trench adjacent to the JFET.
11. The method of claim 9 , wherein the trench is disposed substantially perpendicular to a direction of electric current flow through the channel region of the JFET.
12. The method of claim 9 , wherein the stress-inducing material comprises a silicon nitride stress liner.
13. The method of claim 9 , further comprising etching a top surface of the IC chip such that the stress-inducing material is substantially flush with the top surface of the IC chip.
14. The method of claim 9 , wherein the stress-inducing material imparts a compressive stress in the case that the channel region of the JFET includes p-type dopants, and the stress-inducing material imparts a tensile stress in the case that the channel region of the JFET includes n-type dopants.
15. The method of claim 9 , wherein the at least partially filling includes substantially filling the trench with the stress-inducing material.
16. The method of claim 9 , wherein the horizontal stress imparted on the channel region of the JFET is at least approximately 1 GPa.